8a255b11dd
Signed-off-by: Robert Eckelmann <longnoserob@postmarketos.org> Part-of: <https://gitlab.postmarketos.org/postmarketOS/pmaports/-/merge_requests/7605>
54 lines
2.3 KiB
Diff
54 lines
2.3 KiB
Diff
From 07ad0166548a48002185f74f599a9eae903c6ccd Mon Sep 17 00:00:00 2001
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From: Doug Brown <doug@schmorgal.com>
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Date: Sun, 11 Sep 2022 15:01:47 -0700
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Subject: [PATCH] drm/armada: add optional ability to preserve existing
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framebuffer
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This allows the framebuffer to continue displaying a default image that
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was set up by the bootloader until something else decides to change the
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display.
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Signed-off-by: Doug Brown <doug@schmorgal.com>
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---
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drivers/gpu/drm/armada/armada_crtc.c | 16 ++++++++++++----
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1 file changed, 12 insertions(+), 4 deletions(-)
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diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c
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index f03f91a9384b79..45e20107fc1389 100644
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--- a/drivers/gpu/drm/armada/armada_crtc.c
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+++ b/drivers/gpu/drm/armada/armada_crtc.c
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@@ -919,6 +919,8 @@ static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev,
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void __iomem *base;
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int ret;
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const char *str;
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+ bool preserve_startup_fb = false;
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+ u32 tmp;
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base = devm_ioremap_resource(dev, res);
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if (IS_ERR(base))
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@@ -1010,15 +1012,21 @@ static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev,
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spin_lock_init(&dcrtc->irq_lock);
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dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR;
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+ if (dev->of_node && of_get_property(dev->of_node, "preserve-startup-fb", NULL))
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+ preserve_startup_fb = true;
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+
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/* Initialize some registers which we don't otherwise set */
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- writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV);
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+ if (!preserve_startup_fb)
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+ writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV);
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writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_BLANKCOLOR);
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writel_relaxed(dcrtc->spu_iopad_ctrl,
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dcrtc->base + LCD_SPU_IOPAD_CONTROL);
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writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_SRAM_PARA0);
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- writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
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- CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 |
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- CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1);
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+ tmp = CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
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+ CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66;
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+ if (!preserve_startup_fb)
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+ tmp |= CFG_PDWN64x66;
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+ writel_relaxed(tmp, dcrtc->base + LCD_SPU_SRAM_PARA1);
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writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1);
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writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
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readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR);
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