8a255b11dd
Signed-off-by: Robert Eckelmann <longnoserob@postmarketos.org> Part-of: <https://gitlab.postmarketos.org/postmarketOS/pmaports/-/merge_requests/7605>
82 lines
3.1 KiB
Diff
82 lines
3.1 KiB
Diff
From 9ecac522c382f34010b283b1617b922725c263c9 Mon Sep 17 00:00:00 2001
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From: Doug Brown <doug@schmorgal.com>
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Date: Thu, 1 Sep 2022 22:44:10 -0700
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Subject: [PATCH] drm/armada: make output format and pin allocation
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configurable
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The output format and pin allocation were previously hardcoded for
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RGB888. This allows you to configure it in device tree.
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Signed-off-by: Doug Brown <doug@schmorgal.com>
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---
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drivers/gpu/drm/armada/armada_crtc.c | 50 +++++++++++++++++++++++++++-
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1 file changed, 49 insertions(+), 1 deletion(-)
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diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c
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index daff098127c56f..f03f91a9384b79 100644
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--- a/drivers/gpu/drm/armada/armada_crtc.c
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+++ b/drivers/gpu/drm/armada/armada_crtc.c
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@@ -918,6 +918,7 @@ static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev,
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struct drm_bridge *bridge;
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void __iomem *base;
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int ret;
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+ const char *str;
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base = devm_ioremap_resource(dev, res);
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if (IS_ERR(base))
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@@ -958,7 +959,54 @@ static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev,
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dcrtc->base = base;
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dcrtc->num = drm->mode_config.num_crtc;
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dcrtc->cfg_dumb_ctrl = DUMB24_RGB888_0;
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- dcrtc->spu_iopad_ctrl = CFG_VSCALE_LN_EN | CFG_IOPAD_DUMB24;
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+ dcrtc->spu_iopad_ctrl = CFG_IOPAD_DUMB24;
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+ if (dev->of_node && !of_property_read_string(dev->of_node, "output-format", &str)) {
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+ if (!strcmp(str, "rgb565_15:0"))
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+ dcrtc->cfg_dumb_ctrl = DUMB16_RGB565_0;
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+ else if (!strcmp(str, "rgb565_23:8"))
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+ dcrtc->cfg_dumb_ctrl = DUMB16_RGB565_1;
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+ else if (!strcmp(str, "rgb666_17:0"))
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+ dcrtc->cfg_dumb_ctrl = DUMB18_RGB666_0;
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+ else if (!strcmp(str, "rgb666_23:6"))
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+ dcrtc->cfg_dumb_ctrl = DUMB18_RGB666_1;
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+ else if (!strcmp(str, "rgb444_11:0"))
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+ dcrtc->cfg_dumb_ctrl = DUMB12_RGB444_0;
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+ else if (!strcmp(str, "rgb444_23:12"))
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+ dcrtc->cfg_dumb_ctrl = DUMB12_RGB444_1;
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+ else if (!strcmp(str, "rgb888"))
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+ dcrtc->cfg_dumb_ctrl = DUMB24_RGB888_0;
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+ else {
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+ DRM_ERROR("invalid output-format specified\n");
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+ ret = -EINVAL;
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+ goto err_crtc;
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+ }
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+ }
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+ if (dev->of_node && !of_property_read_string(dev->of_node, "io-pin-allocation", &str)) {
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+ if (!strcmp(str, "dumb_24"))
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+ dcrtc->spu_iopad_ctrl = CFG_IOPAD_DUMB24;
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+ else if (!strcmp(str, "dumb_18_spi"))
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+ dcrtc->spu_iopad_ctrl = CFG_IOPAD_DUMB18SPI;
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+ else if (!strcmp(str, "dumb_18_gpio"))
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+ dcrtc->spu_iopad_ctrl = CFG_IOPAD_DUMB18GPIO;
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+ else if (!strcmp(str, "dumb_16_spi"))
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+ dcrtc->spu_iopad_ctrl = CFG_IOPAD_DUMB16SPI;
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+ else if (!strcmp(str, "dumb_16_gpio"))
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+ dcrtc->spu_iopad_ctrl = CFG_IOPAD_DUMB16GPIO;
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+ else if (!strcmp(str, "dumb_12"))
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+ dcrtc->spu_iopad_ctrl = CFG_IOPAD_DUMB12GPIO;
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+ else if (!strcmp(str, "smart_18_spi"))
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+ dcrtc->spu_iopad_ctrl = CFG_IOPAD_SMART18;
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+ else if (!strcmp(str, "smart_16_spi"))
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+ dcrtc->spu_iopad_ctrl = CFG_IOPAD_SMART16;
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+ else if (!strcmp(str, "smart_8"))
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+ dcrtc->spu_iopad_ctrl = CFG_IOPAD_SMART8;
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+ else {
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+ DRM_ERROR("invalid io-pin-allocation specified\n");
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+ ret = -EINVAL;
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+ goto err_crtc;
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+ }
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+ }
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+ dcrtc->spu_iopad_ctrl |= CFG_VSCALE_LN_EN;
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spin_lock_init(&dcrtc->irq_lock);
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dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR;
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