linux-postmarketos-mediatek-mt8183: drop aport
Part-of: https://gitlab.postmarketos.org/postmarketOS/pmaports/-/merge_requests/6552 [ci:skip-build]: already built successfully in CI
This commit is contained in:
WeirdTreeThing
Clayton Craft
parent
9539bf687b
commit
bb57bd6b80
9 changed files with 0 additions and 9720 deletions
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@ -1,93 +0,0 @@
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# Maintainer: WeirdTreeThing <bradyn127@protonmail.com>
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# Co-Maintainer: Jenneron <jenneron@protonmail.com>
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pkgname=linux-postmarketos-mediatek-mt8183
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pkgver=6.12.21
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pkgrel=1
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pkgdesc="Mainline kernel for mediatek mt8183"
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arch="aarch64"
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_flavor="${pkgname#linux-}"
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url="https://kernel.org"
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license="GPL-2.0-only"
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options="!strip !check !tracedeps
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pmb:cross-native
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pmb:kconfigcheck-community
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"
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makedepends="
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bison
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devicepkg-dev
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findutils
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flex
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postmarketos-installkernel
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openssl-dev
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perl
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rsync
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gzip
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xz
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gmp-dev
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mpc1-dev
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mpfr-dev
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lz4
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zstd
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"
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replaces="linux-postmarketos-mtk-mt8183"
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_carch="arm64"
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# Source
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_config="config-$_flavor.$CARCH"
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case $pkgver in
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*.*.*) _kernver=${pkgver%.0};;
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*.*) _kernver=$pkgver;;
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esac
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source="
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https://cdn.kernel.org/pub/linux/kernel/v${_kernver%%.*}.x/linux-$_kernver.tar.xz
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arm64-dts-mt8183-Add-kukui-jacuzzi-cerise-board.patch
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drm-mediatek-only-announce-AFBC-if-really-supported.patch
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mt8183-fix-bluetooth.patch
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mt8183-kukui-add-it6505-and-enable-dpi.patch
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mt8183-kukui-jacuzzi-fix-display-resume.patch
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mt8183-kukui-jacuzzi-hack-dpms-resume.patch
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mt8183-kukui-jacuzzi-fennel14-rt1015p-sound.patch
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config-$_flavor.aarch64
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"
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builddir="$srcdir/linux-$_kernver"
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prepare() {
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default_prepare
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cp "$srcdir/config-$_flavor.$CARCH" .config
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}
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build() {
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unset LDFLAGS
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make ARCH="$_carch" \
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KBUILD_BUILD_VERSION="$((pkgrel + 1 ))-$_flavor"
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}
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package() {
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mkdir -p "$pkgdir"/boot
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make zinstall modules_install dtbs_install \
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ARCH="$_carch" \
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INSTALL_PATH="$pkgdir"/boot \
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INSTALL_MOD_PATH="$pkgdir" \
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INSTALL_MOD_STRIP=1 \
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INSTALL_DTBS_PATH="$pkgdir"/boot/dtbs
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rm -f "$pkgdir"/lib/modules/*/build "$pkgdir"/lib/modules/*/source
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install -D "$builddir"/include/config/kernel.release \
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"$pkgdir"/usr/share/kernel/$_flavor/kernel.release
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}
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sha512sums="
|
||||
14436c71264c8679a1a9aada6b64d916a6ac5ff5f2128b344e844bea41780832b9bb5c74ee7d0970ee84b02feff433b1003303e129ff26deaba705aff3608b6f linux-6.12.21.tar.xz
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||||
a95ce4a71d249ef401ca04cf8faf85b9022114d35fef5a0ce18929f734a0ac80ed0332648cc9768625f3c26b3720679e1a20bf8ac564087bd4c64f49cd96cc45 arm64-dts-mt8183-Add-kukui-jacuzzi-cerise-board.patch
|
||||
d74da1231181835bec82015da1b3f5b08a1fe9c3c35dd712e285891094d94d9427ceac75d32f74be3a635e17d93ad82b37adf97db8176efc91aed17535023fc2 mt8183-fix-bluetooth.patch
|
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19fdf640c34a0c04ba6aca85e93650f8696fe16d2fd2dba2a79ed504c5e2813868f5dfd91f9b3ee6951eede2b2b1e295c7a0c0f5b462996316b4576973c82ddd mt8183-kukui-add-it6505-and-enable-dpi.patch
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519b6468bca78d0e315c826592ae40dddca9daeba7c2b451a20ca996494cca45721833b9138fefbb543f53e0b9257c78ec4fec54de2a160aa8df730daf3ac996 mt8183-kukui-jacuzzi-fix-display-resume.patch
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e9a128a8ddd98c6c8957ba45186afa2ea8ebeac83d4f2db3ff9ee8a5dd8027af90868c334a7b456bfe7dce793517f27ad63efa220bc933e3407f6362da6d7b2a mt8183-kukui-jacuzzi-hack-dpms-resume.patch
|
||||
9b8707de42635734031495da055c5860addeb656051540f1a14404b10aa8b501168d8b0e274b37bce989db3bc050e9beef722189556f6d782b92cc907731488d mt8183-kukui-jacuzzi-fennel14-rt1015p-sound.patch
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c133230bc7023531cee932e0a007613b9813ccaec422a0e9d9ff14e6afb6f6cc82a774a45668ff1777d8746e25938fcd40194419c2945f0700a7aef3c3c0f488 drm-mediatek-only-announce-AFBC-if-really-supported.patch
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ce12fb0bf44817398d19d937776f4484fa3e17952852f242273fb125c2af2a1a3bddcec27bf66cb965806c92aafed660b979920ab027f0e3a635f682b594d277 config-postmarketos-mediatek-mt8183.aarch64
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"
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@ -1,181 +0,0 @@
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diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
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index ebef3873e..93523a22d 100644
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--- a/arch/arm64/boot/dts/mediatek/Makefile
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+++ b/arch/arm64/boot/dts/mediatek/Makefile
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@@ -22,6 +22,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana-rev7.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-burnet.dtb
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+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-cerise.dtb
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+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-cerise-rev3.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-cozmo.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-damu.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku1.dtb
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@@ -32,6 +34,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel14-sku2.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-juniper-sku16.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kappa.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kenzo.dtb
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+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-stern.dtb
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+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-stern-rev3.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-makomo-sku0.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-makomo-sku1.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-pico.dtb
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diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cerise-rev3.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cerise-rev3.dts
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new file mode 100644
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index 000000000..2776d9356
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--- /dev/null
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+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cerise-rev3.dts
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@@ -0,0 +1,24 @@
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+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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+/*
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+ * Copyright 2021 Google LLC
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+ */
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+
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+/dts-v1/;
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+#include "mt8183-kukui-jacuzzi-cerise.dtsi"
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+
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+/ {
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+ model = "Google cerise board";
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+ compatible = "google,cerise-rev3-sku0", "google,cerise", "mediatek,mt8183";
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+};
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+
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+&mt6358codec {
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+ mediatek,dmic-mode = <1>; /* one-wire */
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+};
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+
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+&touchscreen {
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+ status = "disabled";
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+};
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+
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+&qca_wifi {
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+ qcom,ath10k-calibration-variant = "GO_CERISE";
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+};
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diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cerise.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cerise.dts
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new file mode 100644
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index 000000000..418b5024d
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--- /dev/null
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+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cerise.dts
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@@ -0,0 +1,24 @@
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+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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+/*
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+ * Copyright 2021 Google LLC
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+ */
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+
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+/dts-v1/;
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+#include "mt8183-kukui-jacuzzi-cerise.dtsi"
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+
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+/ {
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+ model = "Google cerise board";
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+ compatible = "google,cerise-sku0", "google,cerise", "mediatek,mt8183";
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+};
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+
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+&mt6358codec {
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+ mediatek,dmic-mode = <1>; /* one-wire */
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+};
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+
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+&touchscreen {
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+ status = "disabled";
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+};
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+
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+&qca_wifi {
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+ qcom,ath10k-calibration-variant = "GO_CERISE";
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+};
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diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cerise.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cerise.dtsi
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new file mode 100644
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index 000000000..ec1561ac3
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--- /dev/null
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+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cerise.dtsi
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@@ -0,0 +1,13 @@
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+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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+/*
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+ * Copyright 2021 Google LLC
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+ */
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+
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+/dts-v1/;
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+#include "mt8183-kukui-jacuzzi.dtsi"
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+
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+&mmc1_pins_uhs {
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+ pins_clk {
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+ drive-strength = <MTK_DRIVE_6mA>;
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+ };
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+};
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diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-stern-rev3.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-stern-rev3.dts
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new file mode 100644
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index 000000000..05303c4ed
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--- /dev/null
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+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-stern-rev3.dts
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@@ -0,0 +1,34 @@
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+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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+/*
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+ * Copyright 2021 Google LLC
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+ */
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+
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+/dts-v1/;
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+#include "mt8183-kukui-jacuzzi-cerise.dtsi"
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+
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+/ {
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+ model = "Google stern board";
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+ compatible = "google,cerise-rev3-sku1", "google,cerise", "mediatek,mt8183";
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+};
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+
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+&mt6358codec {
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+ mediatek,dmic-mode = <0>; /* two-wire */
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+};
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+
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+&touchscreen {
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+ status = "okay";
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+
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+ compatible = "hid-over-i2c";
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+ reg = <0x10>;
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+ interrupt-parent = <&pio>;
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+ interrupts = <155 IRQ_TYPE_LEVEL_LOW>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&touchscreen_pins>;
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+
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+ post-power-on-delay-ms = <10>;
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+ hid-descr-addr = <0x0001>;
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+};
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+
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+&qca_wifi {
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+ qcom,ath10k-calibration-variant = "GO_STERN";
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+};
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diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-stern.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-stern.dts
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new file mode 100644
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index 000000000..5be767bc8
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--- /dev/null
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+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-stern.dts
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@@ -0,0 +1,34 @@
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+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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+/*
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+ * Copyright 2021 Google LLC
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+ */
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+
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+/dts-v1/;
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+#include "mt8183-kukui-jacuzzi-cerise.dtsi"
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+
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+/ {
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+ model = "Google stern board";
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+ compatible = "google,cerise-sku1", "google,cerise", "mediatek,mt8183";
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+};
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+
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+&mt6358codec {
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+ mediatek,dmic-mode = <0>; /* two-wire */
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+};
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+
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+&touchscreen {
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+ status = "okay";
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+
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+ compatible = "hid-over-i2c";
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+ reg = <0x10>;
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+ interrupt-parent = <&pio>;
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+ interrupts = <155 IRQ_TYPE_LEVEL_LOW>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&touchscreen_pins>;
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+
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+ post-power-on-delay-ms = <10>;
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+ hid-descr-addr = <0x0001>;
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+};
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+
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+&qca_wifi {
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+ qcom,ath10k-calibration-variant = "GO_STERN";
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+};
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File diff suppressed because it is too large
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|
||||
pDN7a/Fg4NJDBg08WhNoIZVWGrk5icvYU1dIdY0i5JGzDHZMTNbc02NwwVrcrOjrfsu
|
||||
S6zyJtNrwZ6dlY7A8PQrXktKqw5tUtnwH/HnurkA6i+2DCNFNJVnmFfA7JpMYCKAyZQ
|
||||
5RWarM3/2N9QwVNiLWKLWuCmIBrCiRcrpjDVMCwh6qdhwchqP0RYiiRp/nJ4Y5lVvIO
|
||||
+h8QjqcBiQ==
|
||||
Received: by mx.zohomail.com with SMTPS id 1748693516762703.3998524129344;
|
||||
Sat, 31 May 2025 05:11:56 -0700 (PDT)
|
||||
From: Icenowy Zheng <uwu@icenowy.me>
|
||||
To: Chun-Kuang Hu <chunkuang.hu@kernel.org>,
|
||||
Philipp Zabel <p.zabel@pengutronix.de>, David Airlie <airlied@gmail.com>,
|
||||
Simona Vetter <simona@ffwll.ch>, Matthias Brugger <matthias.bgg@gmail.com>,
|
||||
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
|
||||
Justin Green <greenjustin@chromium.org>
|
||||
Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org,
|
||||
linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
|
||||
Icenowy Zheng <uwu@icenowy.me>
|
||||
Subject: [PATCH] drm/mediatek: only announce AFBC if really supported
|
||||
Date: Sat, 31 May 2025 20:11:40 +0800
|
||||
Message-ID: <20250531121140.387661-1-uwu@icenowy.me>
|
||||
X-Mailer: git-send-email 2.49.0
|
||||
MIME-Version: 1.0
|
||||
X-ZohoMailClient: External
|
||||
X-ZohoMail-Owner: <20250531121140.387661-1-uwu@icenowy.me>+zmo_0_
|
||||
X-BeenThere: dri-devel@lists.freedesktop.org
|
||||
X-Mailman-Version: 2.1.29
|
||||
Precedence: list
|
||||
List-Id: Direct Rendering Infrastructure - Development
|
||||
<dri-devel.lists.freedesktop.org>
|
||||
List-Unsubscribe: <https://lists.freedesktop.org/mailman/options/dri-devel>,
|
||||
<mailto:dri-devel-request@lists.freedesktop.org?subject=unsubscribe>
|
||||
List-Archive: <https://lists.freedesktop.org/archives/dri-devel>
|
||||
List-Post: <mailto:dri-devel@lists.freedesktop.org>
|
||||
List-Help: <mailto:dri-devel-request@lists.freedesktop.org?subject=help>
|
||||
List-Subscribe: <https://lists.freedesktop.org/mailman/listinfo/dri-devel>,
|
||||
<mailto:dri-devel-request@lists.freedesktop.org?subject=subscribe>
|
||||
Errors-To: dri-devel-bounces@lists.freedesktop.org
|
||||
Sender: "dri-devel" <dri-devel-bounces@lists.freedesktop.org>
|
||||
|
||||
Currently even the SoC's OVL does not declare the support of AFBC, AFBC
|
||||
is still announced to the userspace within the IN_FORMATS blob, which
|
||||
breaks modern Wayland compositors like KWin Wayland and others.
|
||||
|
||||
Gate passing modifiers to drm_universal_plane_init() behind querying the
|
||||
driver of the hardware block for AFBC support.
|
||||
|
||||
Fixes: c410fa9b07c3 ("drm/mediatek: Add AFBC support to Mediatek DRM driver")
|
||||
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
|
||||
---
|
||||
Patch tested on MT8183, on which KWin Wayland 5.27.12 is fixed.
|
||||
|
||||
In addition, I tried to fake supports_afbc in mt8183_ovl_driver_data and
|
||||
mt8183_ovl_2l_driver_data, then KWin Wayland gets broken again and
|
||||
modetest also shows the AFBC modifier in IN_FORMATS.
|
||||
|
||||
drivers/gpu/drm/mediatek/mtk_crtc.c | 3 ++-
|
||||
drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 1 +
|
||||
drivers/gpu/drm/mediatek/mtk_ddp_comp.h | 9 +++++++++
|
||||
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 1 +
|
||||
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 7 +++++++
|
||||
drivers/gpu/drm/mediatek/mtk_plane.c | 7 +++++--
|
||||
drivers/gpu/drm/mediatek/mtk_plane.h | 3 ++-
|
||||
7 files changed, 27 insertions(+), 4 deletions(-)
|
||||
|
||||
diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.c b/drivers/gpu/drm/mediatek/mtk_crtc.c
|
||||
index 8f6fba4217ece..53359c2465b65 100644
|
||||
--- a/drivers/gpu/drm/mediatek/mtk_crtc.c
|
||||
+++ b/drivers/gpu/drm/mediatek/mtk_crtc.c
|
||||
@@ -930,7 +930,8 @@ static int mtk_crtc_init_comp_planes(struct drm_device *drm_dev,
|
||||
mtk_ddp_comp_supported_rotations(comp),
|
||||
mtk_ddp_comp_get_blend_modes(comp),
|
||||
mtk_ddp_comp_get_formats(comp),
|
||||
- mtk_ddp_comp_get_num_formats(comp), i);
|
||||
+ mtk_ddp_comp_get_num_formats(comp),
|
||||
+ mtk_ddp_comp_is_afbc_supported(comp), i);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
|
||||
index edc6417639e64..ac6620e10262e 100644
|
||||
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
|
||||
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
|
||||
@@ -366,6 +366,7 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = {
|
||||
.get_blend_modes = mtk_ovl_get_blend_modes,
|
||||
.get_formats = mtk_ovl_get_formats,
|
||||
.get_num_formats = mtk_ovl_get_num_formats,
|
||||
+ .is_afbc_supported = mtk_ovl_is_afbc_supported,
|
||||
};
|
||||
|
||||
static const struct mtk_ddp_comp_funcs ddp_postmask = {
|
||||
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
|
||||
index 39720b27f4e9e..7289b3dcf22f2 100644
|
||||
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
|
||||
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
|
||||
@@ -83,6 +83,7 @@ struct mtk_ddp_comp_funcs {
|
||||
u32 (*get_blend_modes)(struct device *dev);
|
||||
const u32 *(*get_formats)(struct device *dev);
|
||||
size_t (*get_num_formats)(struct device *dev);
|
||||
+ bool (*is_afbc_supported)(struct device *dev);
|
||||
void (*connect)(struct device *dev, struct device *mmsys_dev, unsigned int next);
|
||||
void (*disconnect)(struct device *dev, struct device *mmsys_dev, unsigned int next);
|
||||
void (*add)(struct device *dev, struct mtk_mutex *mutex);
|
||||
@@ -294,6 +295,14 @@ size_t mtk_ddp_comp_get_num_formats(struct mtk_ddp_comp *comp)
|
||||
return 0;
|
||||
}
|
||||
|
||||
+static inline bool mtk_ddp_comp_is_afbc_supported(struct mtk_ddp_comp *comp)
|
||||
+{
|
||||
+ if (comp->funcs && comp->funcs->is_afbc_supported)
|
||||
+ return comp->funcs->is_afbc_supported(comp->dev);
|
||||
+
|
||||
+ return false;
|
||||
+}
|
||||
+
|
||||
static inline bool mtk_ddp_comp_add(struct mtk_ddp_comp *comp, struct mtk_mutex *mutex)
|
||||
{
|
||||
if (comp->funcs && comp->funcs->add) {
|
||||
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
|
||||
index 04217a36939cd..679d413bf10be 100644
|
||||
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
|
||||
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
|
||||
@@ -106,6 +106,7 @@ void mtk_ovl_disable_vblank(struct device *dev);
|
||||
u32 mtk_ovl_get_blend_modes(struct device *dev);
|
||||
const u32 *mtk_ovl_get_formats(struct device *dev);
|
||||
size_t mtk_ovl_get_num_formats(struct device *dev);
|
||||
+bool mtk_ovl_is_afbc_supported(struct device *dev);
|
||||
|
||||
void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex);
|
||||
void mtk_ovl_adaptor_remove_comp(struct device *dev, struct mtk_mutex *mutex);
|
||||
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
|
||||
index d0581c4e3c999..e0236353d4997 100644
|
||||
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
|
||||
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
|
||||
@@ -236,6 +236,13 @@ size_t mtk_ovl_get_num_formats(struct device *dev)
|
||||
return ovl->data->num_formats;
|
||||
}
|
||||
|
||||
+bool mtk_ovl_is_afbc_supported(struct device *dev)
|
||||
+{
|
||||
+ struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
|
||||
+
|
||||
+ return ovl->data->supports_afbc;
|
||||
+}
|
||||
+
|
||||
int mtk_ovl_clk_enable(struct device *dev)
|
||||
{
|
||||
struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
|
||||
diff --git a/drivers/gpu/drm/mediatek/mtk_plane.c b/drivers/gpu/drm/mediatek/mtk_plane.c
|
||||
index 655106bbb76d3..e08b771bc25e9 100644
|
||||
--- a/drivers/gpu/drm/mediatek/mtk_plane.c
|
||||
+++ b/drivers/gpu/drm/mediatek/mtk_plane.c
|
||||
@@ -321,7 +321,8 @@ static const struct drm_plane_helper_funcs mtk_plane_helper_funcs = {
|
||||
int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane,
|
||||
unsigned long possible_crtcs, enum drm_plane_type type,
|
||||
unsigned int supported_rotations, const u32 blend_modes,
|
||||
- const u32 *formats, size_t num_formats, unsigned int plane_idx)
|
||||
+ const u32 *formats, size_t num_formats,
|
||||
+ bool supports_afbc, unsigned int plane_idx)
|
||||
{
|
||||
int err;
|
||||
|
||||
@@ -332,7 +333,9 @@ int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane,
|
||||
|
||||
err = drm_universal_plane_init(dev, plane, possible_crtcs,
|
||||
&mtk_plane_funcs, formats,
|
||||
- num_formats, modifiers, type, NULL);
|
||||
+ num_formats,
|
||||
+ supports_afbc ? modifiers : NULL,
|
||||
+ type, NULL);
|
||||
if (err) {
|
||||
DRM_ERROR("failed to initialize plane\n");
|
||||
return err;
|
||||
diff --git a/drivers/gpu/drm/mediatek/mtk_plane.h b/drivers/gpu/drm/mediatek/mtk_plane.h
|
||||
index 3b13b89989c7e..95c5fa5295d8a 100644
|
||||
--- a/drivers/gpu/drm/mediatek/mtk_plane.h
|
||||
+++ b/drivers/gpu/drm/mediatek/mtk_plane.h
|
||||
@@ -49,5 +49,6 @@ to_mtk_plane_state(struct drm_plane_state *state)
|
||||
int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane,
|
||||
unsigned long possible_crtcs, enum drm_plane_type type,
|
||||
unsigned int supported_rotations, const u32 blend_modes,
|
||||
- const u32 *formats, size_t num_formats, unsigned int plane_idx);
|
||||
+ const u32 *formats, size_t num_formats,
|
||||
+ bool supports_afbc, unsigned int plane_idx);
|
||||
#endif
|
||||
|
|
@ -1,93 +0,0 @@
|
|||
this reverts drivers/tty/serial/8250/8250_mtk.c back to the v5.17 version
|
||||
as otherwise it breaks bluetooth on mt8183 kukui devices
|
||||
|
||||
diff --git a/drivers/tty/serial/8250/8250_mtk.c b/drivers/tty/serial/8250/8250_mtk.c
|
||||
index 54051ec7b499..fb65dc601b23 100644
|
||||
--- a/drivers/tty/serial/8250/8250_mtk.c
|
||||
+++ b/drivers/tty/serial/8250/8250_mtk.c
|
||||
@@ -37,7 +37,6 @@
|
||||
#define MTK_UART_IER_RTSI 0x40 /* Enable RTS Modem status interrupt */
|
||||
#define MTK_UART_IER_CTSI 0x80 /* Enable CTS Modem status interrupt */
|
||||
|
||||
-#define MTK_UART_EFR 38 /* I/O: Extended Features Register */
|
||||
#define MTK_UART_EFR_EN 0x10 /* Enable enhancement feature */
|
||||
#define MTK_UART_EFR_RTS 0x40 /* Enable hardware rx flow control */
|
||||
#define MTK_UART_EFR_CTS 0x80 /* Enable hardware tx flow control */
|
||||
@@ -54,9 +53,6 @@
|
||||
#define MTK_UART_TX_TRIGGER 1
|
||||
#define MTK_UART_RX_TRIGGER MTK_UART_RX_SIZE
|
||||
|
||||
-#define MTK_UART_XON1 40 /* I/O: Xon character 1 */
|
||||
-#define MTK_UART_XOFF1 42 /* I/O: Xoff character 1 */
|
||||
-
|
||||
#ifdef CONFIG_SERIAL_8250_DMA
|
||||
enum dma_rx_status {
|
||||
DMA_RX_START = 0,
|
||||
@@ -173,7 +169,7 @@ static void mtk8250_dma_enable(struct uart_8250_port *up)
|
||||
MTK_UART_DMA_EN_RX | MTK_UART_DMA_EN_TX);
|
||||
|
||||
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
|
||||
- serial_out(up, MTK_UART_EFR, UART_EFR_ECB);
|
||||
+ serial_out(up, UART_EFR, UART_EFR_ECB);
|
||||
serial_out(up, UART_LCR, lcr);
|
||||
|
||||
if (dmaengine_slave_config(dma->rxchan, &dma->rxconf) != 0)
|
||||
@@ -236,7 +232,7 @@ static void mtk8250_set_flow_ctrl(struct uart_8250_port *up, int mode)
|
||||
int lcr = serial_in(up, UART_LCR);
|
||||
|
||||
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
|
||||
- serial_out(up, MTK_UART_EFR, UART_EFR_ECB);
|
||||
+ serial_out(up, UART_EFR, UART_EFR_ECB);
|
||||
serial_out(up, UART_LCR, lcr);
|
||||
lcr = serial_in(up, UART_LCR);
|
||||
|
||||
@@ -245,7 +241,7 @@ static void mtk8250_set_flow_ctrl(struct uart_8250_port *up, int mode)
|
||||
serial_out(up, MTK_UART_ESCAPE_DAT, MTK_UART_ESCAPE_CHAR);
|
||||
serial_out(up, MTK_UART_ESCAPE_EN, 0x00);
|
||||
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
|
||||
- serial_out(up, MTK_UART_EFR, serial_in(up, MTK_UART_EFR) &
|
||||
+ serial_out(up, UART_EFR, serial_in(up, UART_EFR) &
|
||||
(~(MTK_UART_EFR_HW_FC | MTK_UART_EFR_SW_FC_MASK)));
|
||||
serial_out(up, UART_LCR, lcr);
|
||||
mtk8250_disable_intrs(up, MTK_UART_IER_XOFFI |
|
||||
@@ -259,8 +255,8 @@ static void mtk8250_set_flow_ctrl(struct uart_8250_port *up, int mode)
|
||||
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
|
||||
|
||||
/*enable hw flow control*/
|
||||
- serial_out(up, MTK_UART_EFR, MTK_UART_EFR_HW_FC |
|
||||
- (serial_in(up, MTK_UART_EFR) &
|
||||
+ serial_out(up, UART_EFR, MTK_UART_EFR_HW_FC |
|
||||
+ (serial_in(up, UART_EFR) &
|
||||
(~(MTK_UART_EFR_HW_FC | MTK_UART_EFR_SW_FC_MASK))));
|
||||
|
||||
serial_out(up, UART_LCR, lcr);
|
||||
@@ -274,12 +270,12 @@ static void mtk8250_set_flow_ctrl(struct uart_8250_port *up, int mode)
|
||||
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
|
||||
|
||||
/*enable sw flow control */
|
||||
- serial_out(up, MTK_UART_EFR, MTK_UART_EFR_XON1_XOFF1 |
|
||||
- (serial_in(up, MTK_UART_EFR) &
|
||||
+ serial_out(up, UART_EFR, MTK_UART_EFR_XON1_XOFF1 |
|
||||
+ (serial_in(up, UART_EFR) &
|
||||
(~(MTK_UART_EFR_HW_FC | MTK_UART_EFR_SW_FC_MASK))));
|
||||
|
||||
- serial_out(up, MTK_UART_XON1, START_CHAR(port->state->port.tty));
|
||||
- serial_out(up, MTK_UART_XOFF1, STOP_CHAR(port->state->port.tty));
|
||||
+ serial_out(up, UART_XON1, START_CHAR(port->state->port.tty));
|
||||
+ serial_out(up, UART_XOFF1, STOP_CHAR(port->state->port.tty));
|
||||
serial_out(up, UART_LCR, lcr);
|
||||
mtk8250_disable_intrs(up, MTK_UART_IER_CTSI|MTK_UART_IER_RTSI);
|
||||
mtk8250_enable_intrs(up, MTK_UART_IER_XOFFI);
|
||||
@@ -293,10 +289,10 @@ static void
|
||||
mtk8250_set_termios(struct uart_port *port, struct ktermios *termios,
|
||||
struct ktermios *old)
|
||||
{
|
||||
- static const unsigned short fraction_L_mapping[] = {
|
||||
+ unsigned short fraction_L_mapping[] = {
|
||||
0, 1, 0x5, 0x15, 0x55, 0x57, 0x57, 0x77, 0x7F, 0xFF, 0xFF
|
||||
};
|
||||
- static const unsigned short fraction_M_mapping[] = {
|
||||
+ unsigned short fraction_M_mapping[] = {
|
||||
0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 3
|
||||
};
|
||||
struct uart_8250_port *up = up_to_u8250p(port);
|
||||
|
|
@ -1,139 +0,0 @@
|
|||
from: https://chromium.googlesource.com/chromiumos/third_party/kernel/+/55500342cfdb02f5550481df77c2d3a541b73e93%5E%21/#F0
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
|
||||
index 8155658..50f84ae 100644
|
||||
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
|
||||
|
||||
@@ -259,6 +259,18 @@ &cpu7 {
|
||||
proc-supply = <&mt6358_vproc11_reg>;
|
||||
};
|
||||
|
||||
+&dpi0 {
|
||||
+ pinctrl-names = "sleep", "default";
|
||||
+ pinctrl-0 = <&dpi_pin_default>;
|
||||
+ pinctrl-1 = <&dpi_pin_func>;
|
||||
+ status = "okay";
|
||||
+ port {
|
||||
+ dpi_out: endpoint {
|
||||
+ remote-endpoint = <&it6505_in>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
&dsi0 {
|
||||
status = "okay";
|
||||
#address-cells = <1>;
|
||||
@@ -321,6 +333,27 @@ &i2c3 {
|
||||
clock-frequency = <100000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
+
|
||||
+ it6505dptx: it6505dptx@5c {
|
||||
+ compatible = "ite,it6505";
|
||||
+ status = "okay";
|
||||
+ interrupt-parent = <&pio>;
|
||||
+ interrupts = <152 IRQ_TYPE_LEVEL_LOW 152 0>;
|
||||
+ reg = <0x5c>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&it6505_pins>;
|
||||
+ ovdd-supply = <&mt6358_vsim2_reg>;
|
||||
+ pwr18-supply = <&it6505_pp18_reg>;
|
||||
+ reset-gpios = <&pio 179 GPIO_ACTIVE_HIGH>;
|
||||
+ hpd-gpios = <&pio 9 0>;
|
||||
+ extcon = <&usbc_extcon>;
|
||||
+ no-laneswap;
|
||||
+ port {
|
||||
+ it6505_in: endpoint {
|
||||
+ remote-endpoint = <&dpi_out>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
@@ -515,6 +548,51 @@ pins_cmd_dat {
|
||||
};
|
||||
};
|
||||
|
||||
+ dpi_pin_default: dpi_pin_default {
|
||||
+ pins_cmd_dat {
|
||||
+ pinmux = <PINMUX_GPIO13__FUNC_GPIO13>,
|
||||
+ <PINMUX_GPIO14__FUNC_GPIO14>,
|
||||
+ <PINMUX_GPIO15__FUNC_GPIO15>,
|
||||
+ <PINMUX_GPIO16__FUNC_GPIO16>,
|
||||
+ <PINMUX_GPIO17__FUNC_GPIO17>,
|
||||
+ <PINMUX_GPIO18__FUNC_GPIO18>,
|
||||
+ <PINMUX_GPIO19__FUNC_GPIO19>,
|
||||
+ <PINMUX_GPIO20__FUNC_GPIO20>,
|
||||
+ <PINMUX_GPIO21__FUNC_GPIO21>,
|
||||
+ <PINMUX_GPIO22__FUNC_GPIO22>,
|
||||
+ <PINMUX_GPIO23__FUNC_GPIO23>,
|
||||
+ <PINMUX_GPIO24__FUNC_GPIO24>,
|
||||
+ <PINMUX_GPIO25__FUNC_GPIO25>,
|
||||
+ <PINMUX_GPIO26__FUNC_GPIO26>,
|
||||
+ <PINMUX_GPIO27__FUNC_GPIO27>,
|
||||
+ <PINMUX_GPIO28__FUNC_GPIO28>;
|
||||
+ drive-strength = <MTK_DRIVE_6mA>;
|
||||
+ output-low;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ dpi_pin_func: dpi_pin_func {
|
||||
+ pins_cmd_dat {
|
||||
+ pinmux = <PINMUX_GPIO13__FUNC_DBPI_D0>,
|
||||
+ <PINMUX_GPIO14__FUNC_DBPI_D1>,
|
||||
+ <PINMUX_GPIO15__FUNC_DBPI_D2>,
|
||||
+ <PINMUX_GPIO16__FUNC_DBPI_D3>,
|
||||
+ <PINMUX_GPIO17__FUNC_DBPI_D4>,
|
||||
+ <PINMUX_GPIO18__FUNC_DBPI_D5>,
|
||||
+ <PINMUX_GPIO19__FUNC_DBPI_D6>,
|
||||
+ <PINMUX_GPIO20__FUNC_DBPI_D7>,
|
||||
+ <PINMUX_GPIO21__FUNC_DBPI_D8>,
|
||||
+ <PINMUX_GPIO22__FUNC_DBPI_D9>,
|
||||
+ <PINMUX_GPIO23__FUNC_DBPI_D10>,
|
||||
+ <PINMUX_GPIO24__FUNC_DBPI_D11>,
|
||||
+ <PINMUX_GPIO25__FUNC_DBPI_HSYNC>,
|
||||
+ <PINMUX_GPIO26__FUNC_DBPI_VSYNC>,
|
||||
+ <PINMUX_GPIO27__FUNC_DBPI_DE>,
|
||||
+ <PINMUX_GPIO28__FUNC_DBPI_CK>;
|
||||
+ drive-strength = <MTK_DRIVE_6mA>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
ec_ap_int_odl: ec-ap-int-odl {
|
||||
pins1 {
|
||||
pinmux = <PINMUX_GPIO151__FUNC_GPIO151>;
|
||||
@@ -586,6 +664,32 @@ pins-bus {
|
||||
};
|
||||
};
|
||||
|
||||
+ it6505_pins: it6505_pins {
|
||||
+ pins_hpd {
|
||||
+ pinmux = <PINMUX_GPIO9__FUNC_GPIO9>;
|
||||
+ input-enable;
|
||||
+ bias-pull-up;
|
||||
+ };
|
||||
+
|
||||
+ pins_int {
|
||||
+ pinmux = <PINMUX_GPIO152__FUNC_GPIO152>;
|
||||
+ input-enable;
|
||||
+ bias-pull-up;
|
||||
+ };
|
||||
+
|
||||
+ pins_power_enable {
|
||||
+ pinmux = <PINMUX_GPIO178__FUNC_GPIO178>;
|
||||
+ output-low;
|
||||
+ bias-pull-up;
|
||||
+ };
|
||||
+
|
||||
+ pins_reset {
|
||||
+ pinmux = <PINMUX_GPIO179__FUNC_GPIO179>;
|
||||
+ output-low;
|
||||
+ bias-pull-up;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
mmc0_pins_default: mmc0-pins-default {
|
||||
pins-cmd-dat {
|
||||
pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
removes a dapm sound route, that prevents loading the kernel module
|
||||
|
||||
--- a/sound/soc/mediatek/mt8183/mt8183-da7219-max98357.c
|
||||
+++ b/sound/soc/mediatek/mt8183/mt8183-da7219-max98357.c
|
||||
@@ -590,7 +590,7 @@
|
||||
|
||||
static const struct snd_soc_dapm_route mt8183_da7219_max98357_dapm_routes[] = {
|
||||
{"Speakers", NULL, "Speaker"},
|
||||
- {"I2S Playback", NULL, "TDM_OUT_PINCTRL"},
|
||||
+// {"I2S Playback", NULL, "TDM_OUT_PINCTRL"},
|
||||
};
|
||||
|
||||
static struct snd_soc_card mt8183_da7219_max98357_card = {
|
||||
|
|
@ -1,63 +0,0 @@
|
|||
from: https://patchwork.kernel.org/project/linux-mediatek/patch/20210720100553.2340425-1-pihsun@chromium.org/
|
||||
[v2] drm/bridge: anx7625: Use pm_runtime_force_{suspend, resume}
|
||||
|
||||
diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c
|
||||
index 14d73fb1dd15..8325e8d0ee19 100644
|
||||
--- a/drivers/gpu/drm/bridge/analogix/anx7625.c
|
||||
+++ b/drivers/gpu/drm/bridge/analogix/anx7625.c
|
||||
@@ -1349,6 +1349,8 @@ static void anx7625_bridge_detach(struct drm_bridge *bridge)
|
||||
mipi_dsi_detach(ctx->dsi);
|
||||
mipi_dsi_device_unregister(ctx->dsi);
|
||||
}
|
||||
+ if (ctx->link)
|
||||
+ device_link_del(ctx->link);
|
||||
}
|
||||
|
||||
static int anx7625_bridge_attach(struct drm_bridge *bridge,
|
||||
@@ -1373,17 +1375,33 @@ static int anx7625_bridge_attach(struct drm_bridge *bridge,
|
||||
return err;
|
||||
}
|
||||
|
||||
+ ctx->link = device_link_add(bridge->dev->dev, dev, DL_FLAG_STATELESS);
|
||||
+ if (!ctx->link) {
|
||||
+ DRM_DEV_ERROR(dev, "device link creation failed");
|
||||
+ err = -EINVAL;
|
||||
+ goto detach_dsi;
|
||||
+ }
|
||||
+
|
||||
if (ctx->pdata.panel_bridge) {
|
||||
err = drm_bridge_attach(bridge->encoder,
|
||||
ctx->pdata.panel_bridge,
|
||||
&ctx->bridge, flags);
|
||||
if (err)
|
||||
- return err;
|
||||
+ goto remove_device_link;
|
||||
}
|
||||
|
||||
ctx->bridge_attached = 1;
|
||||
|
||||
return 0;
|
||||
+
|
||||
+remove_device_link:
|
||||
+ device_link_del(ctx->link);
|
||||
+detach_dsi:
|
||||
+ if (ctx->dsi) {
|
||||
+ mipi_dsi_detach(ctx->dsi);
|
||||
+ mipi_dsi_device_unregister(ctx->dsi);
|
||||
+ }
|
||||
+ return err;
|
||||
}
|
||||
|
||||
static enum drm_mode_status
|
||||
diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.h b/drivers/gpu/drm/bridge/analogix/anx7625.h
|
||||
index edbbfe410a56..299e62df6238 100644
|
||||
--- a/drivers/gpu/drm/bridge/analogix/anx7625.h
|
||||
+++ b/drivers/gpu/drm/bridge/analogix/anx7625.h
|
||||
@@ -473,6 +473,7 @@ struct anx7625_data {
|
||||
struct drm_connector *connector;
|
||||
struct mipi_dsi_device *dsi;
|
||||
struct drm_dp_aux aux;
|
||||
+ struct device_link *link;
|
||||
};
|
||||
|
||||
#endif /* __ANX7625_H__ */
|
||||
|
|
@ -1,16 +0,0 @@
|
|||
this is most probably not the proper solution, but it at least lets the display
|
||||
come back properly after a dpms suspend ...
|
||||
|
||||
diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c
|
||||
index 31ecf5626f1d..6763b280dab4 100644
|
||||
--- a/drivers/gpu/drm/bridge/analogix/anx7625.c
|
||||
+++ b/drivers/gpu/drm/bridge/analogix/anx7625.c
|
||||
@@ -1425,6 +1427,8 @@ static void anx7625_start_dp_work(struct anx7625_data *ctx)
|
||||
return;
|
||||
|
||||
DRM_DEV_DEBUG_DRIVER(dev, "Secure OCM version=%02x\n", ret);
|
||||
+
|
||||
+ ctx->display_timing_valid = 1;
|
||||
}
|
||||
|
||||
static int anx7625_read_hpd_status_p0(struct anx7625_data *ctx)
|
||||
Loading…
Add table
Add a link
Reference in a new issue