From 90281e97225dd13ede14081eedefb6df81c2c8fb Mon Sep 17 00:00:00 2001 From: bluebunny <1812-bluebunny@users.noreply.gitlab.postmarketos.org> Date: Fri, 10 Apr 2026 18:21:30 +0900 Subject: [PATCH] testing/linux-xiaomi-pipa: upgrade to 6.19.11 Part-of: --- ...m8250-xiaomi-pipa-Add-device-tree-fo.patch | 5 +- ...-driver-for-Qualcomm-PMIC-fuel-gauge.patch | 2 +- ...er-supply-add-bq25970-charger-driver.patch | 2 +- ...Input-Add-nt36523-touchscreen-driver.patch | 805 ++++++++--- .../0005-drm-Add-drm-notifier-support.patch | 2 +- ...el-turn-on-off-signal-to-touchscreen.patch | 2 +- ...ge-sync-mode-to-sync-on-DSI0-rather-.patch | 2 +- ...ort-DSC-configurations-with-slice_pe.patch | 10 +- ...dd-support-for-Novatek-NT36532-panel.patch | 1223 +---------------- ...c-ov13b10-add-device-tree-support-an.patch | 2 +- ...cs-aw88261-add-hacks-for-xiaomi-pipa.patch | 533 +------ ...012-ASoC-qcom-sm8250-Add-tdm-support.patch | 2 +- device/testing/linux-xiaomi-pipa/APKBUILD | 30 +- .../config-xiaomi-pipa.aarch64 | 15 +- 14 files changed, 654 insertions(+), 1981 deletions(-) diff --git a/device/testing/linux-xiaomi-pipa/0001-arm64-dts-qcom-sm8250-xiaomi-pipa-Add-device-tree-fo.patch b/device/testing/linux-xiaomi-pipa/0001-arm64-dts-qcom-sm8250-xiaomi-pipa-Add-device-tree-fo.patch index db365a0f2..f59d9c4e7 100644 --- a/device/testing/linux-xiaomi-pipa/0001-arm64-dts-qcom-sm8250-xiaomi-pipa-Add-device-tree-fo.patch +++ b/device/testing/linux-xiaomi-pipa/0001-arm64-dts-qcom-sm8250-xiaomi-pipa-Add-device-tree-fo.patch @@ -1,7 +1,8 @@ -From 2b12882b851d1eea3aaa7ad416d0b7de863530e8 Mon Sep 17 00:00:00 2001 +From bf64a74631c1df015388ff572c8479084b625da1 Mon Sep 17 00:00:00 2001 From: bluebunny <1812-bluebunny@users.noreply.gitlab.postmarketos.org> Date: Thu, 19 Mar 2026 14:52:20 +0900 -Subject: [PATCH 01/12] arm64: dts: qcom: sm8250-xiaomi-pipa: Add device tree for Xiaomi Pad 6 +Subject: [PATCH 01/12] arm64: dts: qcom: sm8250-xiaomi-pipa: Add device tree + for Xiaomi Pad 6 Co-developed-by: Ryo Kenrie Wongso Signed-off-by: Ryo Kenrie Wongso diff --git a/device/testing/linux-xiaomi-pipa/0002-power-supply-Add-driver-for-Qualcomm-PMIC-fuel-gauge.patch b/device/testing/linux-xiaomi-pipa/0002-power-supply-Add-driver-for-Qualcomm-PMIC-fuel-gauge.patch index 2d66d876e..bd46037bc 100644 --- a/device/testing/linux-xiaomi-pipa/0002-power-supply-Add-driver-for-Qualcomm-PMIC-fuel-gauge.patch +++ b/device/testing/linux-xiaomi-pipa/0002-power-supply-Add-driver-for-Qualcomm-PMIC-fuel-gauge.patch @@ -1,4 +1,4 @@ -From 7fbd6cbdc9d417ac9f600e946b2a4b695ab84804 Mon Sep 17 00:00:00 2001 +From 8de782658e6f847107e711873af8c7412e1d7299 Mon Sep 17 00:00:00 2001 From: Joel Selvaraj Date: Wed, 3 Feb 2021 19:54:45 +0000 Subject: [PATCH 02/12] power: supply: Add driver for Qualcomm PMIC fuel gauge diff --git a/device/testing/linux-xiaomi-pipa/0003-power-supply-add-bq25970-charger-driver.patch b/device/testing/linux-xiaomi-pipa/0003-power-supply-add-bq25970-charger-driver.patch index 79392c142..948ff273f 100644 --- a/device/testing/linux-xiaomi-pipa/0003-power-supply-add-bq25970-charger-driver.patch +++ b/device/testing/linux-xiaomi-pipa/0003-power-supply-add-bq25970-charger-driver.patch @@ -1,4 +1,4 @@ -From 3bd98bc7ce56ff2472cb17a0be9bcb56b107ac25 Mon Sep 17 00:00:00 2001 +From 154dfbecbae5be661610d14895fffd036bb45b8c Mon Sep 17 00:00:00 2001 From: Jianhua Lu Date: Wed, 18 Sep 2024 14:27:53 +0800 Subject: [PATCH 03/12] power: supply: add bq25970 charger driver diff --git a/device/testing/linux-xiaomi-pipa/0004-Input-Add-nt36523-touchscreen-driver.patch b/device/testing/linux-xiaomi-pipa/0004-Input-Add-nt36523-touchscreen-driver.patch index 54e517f0f..e1aa4adbe 100644 --- a/device/testing/linux-xiaomi-pipa/0004-Input-Add-nt36523-touchscreen-driver.patch +++ b/device/testing/linux-xiaomi-pipa/0004-Input-Add-nt36523-touchscreen-driver.patch @@ -1,4 +1,4 @@ -From 6d8697dfd972fcda03ca3e4a5d2335da010b5fff Mon Sep 17 00:00:00 2001 +From e3ba2e305e2206903c924f0dd4604186ee29c2cb Mon Sep 17 00:00:00 2001 From: Jianhua Lu Date: Thu, 4 Aug 2022 13:26:26 +0800 Subject: [PATCH 04/12] Input: Add nt36523 touchscreen driver @@ -8,11 +8,11 @@ Subject: [PATCH 04/12] Input: Add nt36523 touchscreen driver drivers/input/touchscreen/Makefile | 1 + drivers/input/touchscreen/nt36523/Kconfig | 11 + drivers/input/touchscreen/nt36523/Makefile | 8 + - drivers/input/touchscreen/nt36523/nt36xxx.c | 1910 +++++++++++++++++ - drivers/input/touchscreen/nt36523/nt36xxx.h | 242 +++ - .../touchscreen/nt36523/nt36xxx_fw_update.c | 857 ++++++++ - .../touchscreen/nt36523/nt36xxx_mem_map.h | 390 ++++ - 8 files changed, 3421 insertions(+) + drivers/input/touchscreen/nt36523/nt36xxx.c | 1943 +++++++++++++++++ + drivers/input/touchscreen/nt36523/nt36xxx.h | 261 +++ + .../touchscreen/nt36523/nt36xxx_fw_update.c | 902 ++++++++ + .../touchscreen/nt36523/nt36xxx_mem_map.h | 656 ++++++ + 8 files changed, 3784 insertions(+) create mode 100644 drivers/input/touchscreen/nt36523/Kconfig create mode 100644 drivers/input/touchscreen/nt36523/Makefile create mode 100644 drivers/input/touchscreen/nt36523/nt36xxx.c @@ -75,10 +75,10 @@ index 000000000000..d16afc8f127f + nt36xxx_fw_update.o diff --git a/drivers/input/touchscreen/nt36523/nt36xxx.c b/drivers/input/touchscreen/nt36523/nt36xxx.c new file mode 100644 -index 000000000000..63c584f681d7 +index 000000000000..fc9829a6b6e0 --- /dev/null +++ b/drivers/input/touchscreen/nt36523/nt36xxx.c -@@ -0,0 +1,1910 @@ +@@ -0,0 +1,1943 @@ +/* + * Copyright (C) 2010 - 2018 Novatek, Inc. + * Copyright (C) 2021 XiaoMi, Inc. @@ -321,30 +321,6 @@ index 000000000000..63c584f681d7 + return ret; +} + -+/******************************************************* -+Description: -+ Novatek touchscreen enable hw bld crc function. -+ -+return: -+ N/A. -+*******************************************************/ -+void nvt_bld_crc_enable(void) -+{ -+ uint8_t buf[4] = {0}; -+ -+ //---set xdata index to BLD_CRC_EN_ADDR--- -+ nvt_set_page(ts->mmap->BLD_CRC_EN_ADDR); -+ -+ //---read data from index--- -+ buf[0] = ts->mmap->BLD_CRC_EN_ADDR & (0x7F); -+ buf[1] = 0xFF; -+ CTP_SPI_READ(ts->client, buf, 2); -+ -+ //---write data to index--- -+ buf[0] = ts->mmap->BLD_CRC_EN_ADDR & (0x7F); -+ buf[1] = buf[1] | (0x01 << 7); -+ CTP_SPI_WRITE(ts->client, buf, 2); -+} + +/******************************************************* +Description: @@ -403,10 +379,15 @@ index 000000000000..63c584f681d7 +*******************************************************/ +void nvt_tx_auto_copy_mode(void) +{ -+ //---write TX_AUTO_COPY_EN cmds--- -+ nvt_write_addr(ts->mmap->TX_AUTO_COPY_EN, 0x69); ++ if (ts->auto_copy == CHECK_SPI_DMA_TX_INFO) { ++ //---write TX_AUTO_COPY_EN cmds--- ++ nvt_write_addr(ts->mmap->TX_AUTO_COPY_EN, 0x69); ++ } else if (ts->auto_copy == CHECK_TX_AUTO_COPY_EN) { ++ //---write SPI_MST_AUTO_COPY cmds--- ++ nvt_write_addr(ts->mmap->TX_AUTO_COPY_EN, 0x56); ++ } + -+ NVT_ERR("tx auto copy mode enable\n"); ++ NVT_ERR("tx auto copy mode %d enable\n", ts->auto_copy); +} + +/******************************************************* @@ -688,8 +669,6 @@ index 000000000000..63c584f681d7 + ts->fw_ver = buf[1]; + ts->x_num = buf[3]; + ts->y_num = buf[4]; -+ ts->abs_x_max = (uint16_t)((buf[5] << 8) | buf[6]); -+ ts->abs_y_max = (uint16_t)((buf[7] << 8) | buf[8]); + ts->max_button_num = buf[11]; + ts->cascade = buf[34] & 0x01; + if (ts->pen_support) { @@ -703,8 +682,6 @@ index 000000000000..63c584f681d7 + ts->fw_ver = 0; + ts->x_num = 18; + ts->y_num = 32; -+ ts->abs_x_max = TOUCH_DEFAULT_MAX_WIDTH; -+ ts->abs_y_max = TOUCH_DEFAULT_MAX_HEIGHT; + ts->max_button_num = TOUCH_KEY_NUM; + + if(retry_count < 3) { @@ -803,6 +780,25 @@ index 000000000000..63c584f681d7 + NVT_LOG("spi-max-frequency: %u\n", ts->spi_max_freq); + } + ++ ret = of_property_read_u32(np, "touchscreen-size-x", &ts->abs_x_max); ++ if (ret || ts->abs_x_max == 0) { ++ NVT_LOG("Unable to get screen width\n"); ++ ts->abs_x_max = TOUCH_DEFAULT_MAX_WIDTH; ++ ret = 0; ++ } ++ ++ ret = of_property_read_u32(np, "touchscreen-size-y", &ts->abs_y_max); ++ if (ret || ts->abs_y_max == 0) { ++ NVT_LOG("Unable to get screen height\n"); ++ ts->abs_y_max = TOUCH_DEFAULT_MAX_HEIGHT; ++ ret = 0; ++ } ++ ++ ts->desc = of_device_get_match_data(dev); ++ if (!ts->desc) ++ return -ENODEV; ++ NVT_LOG("Detected input calc type %d\n", ts->desc->input_calc_method); ++ + return ret; +} +#else @@ -934,76 +930,8 @@ index 000000000000..63c584f681d7 +} +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + -+#if NVT_TOUCH_WDT_RECOVERY -+static uint8_t recovery_cnt = 0; -+static uint8_t nvt_wdt_fw_recovery(uint8_t *point_data) -+{ -+ uint32_t recovery_cnt_max = 10; -+ uint8_t recovery_enable = false; -+ uint8_t i = 0; -+ -+ recovery_cnt++; -+ -+ /* check pattern */ -+ for (i=1 ; i<7 ; i++) { -+ if ((point_data[i] != 0xFD) && (point_data[i] != 0xFE)) { -+ recovery_cnt = 0; -+ break; -+ } -+ } -+ -+ if (recovery_cnt > recovery_cnt_max){ -+ recovery_enable = true; -+ recovery_cnt = 0; -+ } -+ -+ return recovery_enable; -+} -+#endif /* #if NVT_TOUCH_WDT_RECOVERY */ -+ +#define PEN_DATA_LEN 14 +#define FW_HISTORY_SIZE 128 -+static uint32_t nvt_dump_fw_history(void) -+{ -+ int32_t ret = 0; -+ uint8_t buf[FW_HISTORY_SIZE + 1 + DUMMY_BYTES] = {0}; -+ int32_t i = 0; -+ char *tmp_dump = NULL; -+ int32_t line_cnt = 0; -+ -+ if (ts->mmap->FW_HISTORY_ADDR == 0) { -+ NVT_ERR("FW_HISTORY_ADDR not available!\n"); -+ ret = -1; -+ goto exit_nvt_dump_fw_history; -+ } -+ nvt_set_page(ts->mmap->FW_HISTORY_ADDR); -+ buf[0] = ts->mmap->FW_HISTORY_ADDR & 0xFF; -+ CTP_SPI_READ(ts->client, buf, FW_HISTORY_SIZE + 1); -+ if (ret) { -+ NVT_ERR("CTP_SPI_READ failed.(%d)\n", ret); -+ ret = -1; -+ goto exit_nvt_dump_fw_history; -+ } -+ -+ tmp_dump = (char *)kzalloc(FW_HISTORY_SIZE * 4, GFP_KERNEL); -+ for (i = 0; i < FW_HISTORY_SIZE; i++) { -+ sprintf(tmp_dump + i * 3 + line_cnt, "%02X ", buf[1 + i]); -+ if ((i + 1) % 16 == 0) { -+ sprintf(tmp_dump + i * 3 + line_cnt + 3, "%c", '\n'); -+ line_cnt++; -+ } -+ } -+ NVT_LOG("%s", tmp_dump); -+ -+exit_nvt_dump_fw_history: -+ if (tmp_dump) { -+ kfree(tmp_dump); -+ tmp_dump = NULL; -+ } -+ nvt_set_page(ts->mmap->EVENT_BUF_ADDR); -+ -+ return ret; -+} + +#define POINT_DATA_LEN 65 +/******************************************************* @@ -1058,26 +986,6 @@ index 000000000000..63c584f681d7 + goto XFER_ERROR; + } + -+ /*--- dump SPI buf --- -+ for (i = 0; i < 10; i++) { -+ NVT_LOG("%02X %02X %02X %02X %02X %02X \n", -+ point_data[1+i*6], point_data[2+i*6], point_data[3+i*6], point_data[4+i*6], point_data[5+i*6], point_data[6+i*6]); -+ } -+ */ -+ -+#if NVT_TOUCH_WDT_RECOVERY -+ /* ESD protect by WDT */ -+ if (nvt_wdt_fw_recovery(point_data)) { -+ NVT_ERR("Recover for fw reset, %02X\n", point_data[1]); -+ if (point_data[1] == 0xFD) { -+ NVT_ERR("Dump FW history:\n"); -+ nvt_dump_fw_history(); -+ } -+ nvt_update_firmware(ts->fw_name); -+ goto XFER_ERROR; -+ } -+#endif /* #if NVT_TOUCH_WDT_RECOVERY */ -+ + /* ESD protect by FW handshake */ + if (nvt_fw_recovery(point_data)) { +#if NVT_TOUCH_ESD_PROTECT @@ -1099,25 +1007,40 @@ index 000000000000..63c584f681d7 + /* update interrupt timer */ + irq_timer = jiffies; +#endif /* #if NVT_TOUCH_ESD_PROTECT */ -+ input_x = (uint32_t)(point_data[position + 1] << 4) + (uint32_t) (point_data[position + 3] >> 4); -+ input_y = (uint32_t)(point_data[position + 2] << 4) + (uint32_t) (point_data[position + 3] & 0x0F); ++ if (ts->desc->input_calc_method == NVT_INPUT_CALC_NT36532) ++ { ++ input_x = (uint32_t)(point_data[position + 1] << 8) + (uint32_t) (point_data[position + 2]); ++ input_y = (uint32_t)(point_data[position + 3] << 8) + (uint32_t) (point_data[position + 4]); ++ } ++ else ++ { ++ input_x = (uint32_t)(point_data[position + 1] << 4) + (uint32_t) (point_data[position + 3] >> 4); ++ input_y = (uint32_t)(point_data[position + 2] << 4) + (uint32_t) (point_data[position + 3] & 0x0F); ++ } + if ((input_x < 0) || (input_y < 0)) + continue; + if ((input_x > ts->abs_x_max) || (input_y > ts->abs_y_max)) + continue; -+ input_w = (uint32_t)(point_data[position + 4]); -+ if (input_w == 0) -+ input_w = 1; -+ if (i < 2) { -+ input_p = (uint32_t)(point_data[position + 5]) + (uint32_t)(point_data[i + 63] << 8); -+ if (input_p > TOUCH_FORCE_NUM) -+ input_p = TOUCH_FORCE_NUM; -+ } else { -+ input_p = (uint32_t)(point_data[position + 5]); ++ if (ts->desc->input_calc_method == NVT_INPUT_CALC_NT36532) ++ { ++ input_w = (uint32_t)(point_data[position + 5]); ++ if (input_w == 0) ++ input_w = 1; ++ input_p = (uint32_t)(point_data[1 + 98 + i]); ++ } ++ else ++ { ++ input_w = (uint32_t)(point_data[position + 4]); ++ if (i < 2) { ++ input_p = (uint32_t)(point_data[position + 5]) + (uint32_t)(point_data[i + 63] << 8); ++ if (input_p > TOUCH_FORCE_NUM) ++ input_p = TOUCH_FORCE_NUM; ++ } else { ++ input_p = (uint32_t)(point_data[position + 5]); ++ } + } + if (input_p == 0) + input_p = 1; -+ +#if MT_PROTOCOL_B + press_id[input_id - 1] = 1; + input_mt_slot(ts->input_dev, input_id - 1); @@ -1247,13 +1170,95 @@ index 000000000000..63c584f681d7 +*******************************************************/ +static int8_t nvt_ts_check_chip_ver_trim(uint32_t chip_ver_trim_addr) +{ -+ -+ ts->mmap = &NT36523_memory_map; -+ ts->carrier_system = NT36523_hw_info.carrier_system; -+ ts->hw_crc = NT36523_hw_info.hw_crc; ++ ts->mmap = ts->desc->mmap; ++ ts->hw_crc = ts->desc->hw_crc; ++ ts->auto_copy = ts->desc->auto_copy; + return 0; +} + ++int32_t nvt_check_tx_auto_copy(void) ++{ ++ uint8_t buf[8] = {0}; ++ int32_t i = 0; ++ const int32_t retry = 200; ++ ++ if (ts->mmap->TX_AUTO_COPY_EN == 0) { ++ NVT_ERR("error, TX_AUTO_COPY_EN = 0\n"); ++ return -1; ++ } ++ ++ for (i = 0; i < retry; i++) { ++ //---set xdata index to SPI_MST_AUTO_COPY--- ++ nvt_set_page(ts->mmap->TX_AUTO_COPY_EN); ++ ++ //---read auto copy status--- ++ buf[0] = ts->mmap->TX_AUTO_COPY_EN & 0x7F; ++ buf[1] = 0xFF; ++ CTP_SPI_READ(ts->client, buf, 2); ++ ++ if (buf[1] == 0x00) ++ break; ++ ++ usleep_range(1000, 1000); ++ } ++ ++ if (i >= retry) { ++ NVT_ERR("failed, i=%d, buf[1]=0x%02X\n", i, buf[1]); ++ return -1; ++ } else { ++ return 0; ++ } ++} ++ ++int32_t nvt_wait_auto_copy(void) ++{ ++ if (ts->auto_copy == CHECK_SPI_DMA_TX_INFO) { ++ return nvt_check_spi_dma_tx_info(); ++ } else if (ts->auto_copy == CHECK_TX_AUTO_COPY_EN) { ++ return nvt_check_tx_auto_copy(); ++ } else { ++ NVT_ERR("failed, not support mode %d!\n", ts->auto_copy); ++ return -1; ++ } ++} ++ ++int32_t disable_pen_input_device(bool disable) { ++ uint8_t buf[8] = {0}; ++ int32_t ret = 0; ++ ++ NVT_LOG("++\n"); ++ if (!bTouchIsAwake || !ts) { ++ NVT_LOG("touch suspend, stop set pen state %s", disable ? "DISABLE" : "ENABLE"); ++ goto nvt_set_pen_enable_out; ++ } ++ ++ msleep(35); ++ disable = (!(ts->pen_input_dev_enable) || ts->pen_is_charge) ? true : disable; ++ ++ //---set xdata index to EVENT BUF ADDR--- ++ ret = nvt_set_page(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_HOST_CMD); ++ if (ret < 0) { ++ NVT_ERR("Set event buffer index fail!\n"); ++ goto nvt_set_pen_enable_out; ++ } ++ ++ buf[0] = EVENT_MAP_HOST_CMD; ++ buf[1] = 0x7B; ++ buf[2] = !!disable; ++ ret = CTP_SPI_WRITE(ts->client, buf, 3); ++ if (ret < 0) { ++ NVT_ERR("set pen %s failed!\n", disable ? "DISABLE" : "ENABLE"); ++ goto nvt_set_pen_enable_out; ++ } ++ NVT_LOG("pen charge state is %s, %s pen input device\n", ++ ts->pen_is_charge ? "ENABLE" : "DISABLE", ++ disable ? "DISABLE" : "ENABLE"); ++ ++nvt_set_pen_enable_out: ++ NVT_LOG("--\n"); ++ return ret; ++} ++ +static void nvt_suspend_work(struct work_struct *work) +{ + struct nvt_ts_data *ts_core = container_of(work, struct nvt_ts_data, suspend_work); @@ -1373,8 +1378,6 @@ index 000000000000..63c584f681d7 + } + } + -+ ts->abs_x_max = TOUCH_DEFAULT_MAX_WIDTH; -+ ts->abs_y_max = TOUCH_DEFAULT_MAX_HEIGHT; + + //---allocate input device--- + ts->input_dev = input_allocate_device(); @@ -1403,8 +1406,6 @@ index 000000000000..63c584f681d7 + ts->y_num = 50; + ts->x_gang_num = 4; + ts->y_gang_num = 6; -+ ts->abs_x_max = TOUCH_DEFAULT_MAX_WIDTH; -+ ts->abs_y_max = TOUCH_DEFAULT_MAX_HEIGHT; + ts->max_button_num = TOUCH_KEY_NUM; + NVT_LOG("Set default fw_ver=%d, x_num=%d, y_num=%d, " + "abs_x_max=%d, abs_y_max=%d, max_button_num=%d!\n", @@ -1465,14 +1466,21 @@ index 000000000000..63c584f681d7 + ts->pen_input_dev->keybit[BIT_WORD(BTN_STYLUS2)] |= BIT_MASK(BTN_STYLUS2); + ts->pen_input_dev->propbit[0] = BIT(INPUT_PROP_DIRECT); + ++ int x_max, y_max; ++ + if (ts->wgp_stylus) { -+ input_set_abs_params(ts->pen_input_dev, ABS_X, 0, ts->abs_x_max * 2 - 1, 0, 0); -+ input_set_abs_params(ts->pen_input_dev, ABS_Y, 0, ts->abs_y_max * 2 - 1, 0, 0); ++ x_max = ts->abs_x_max * 2 - 1; ++ y_max = ts->abs_y_max * 2 - 1; + } else { -+ input_set_abs_params(ts->pen_input_dev, ABS_X, 0, ts->abs_x_max - 1, 0, 0); -+ input_set_abs_params(ts->pen_input_dev, ABS_Y, 0, ts->abs_y_max - 1, 0, 0); ++ x_max = ts->abs_x_max - 1; ++ y_max = ts->abs_y_max - 1; + } + ++ input_set_abs_params(ts->pen_input_dev, ABS_X, 0, x_max, 0, 0); ++ input_set_abs_params(ts->pen_input_dev, ABS_Y, 0, y_max , 0, 0); ++ input_abs_set_res(ts->pen_input_dev, ABS_X, x_max / PANEL_DEFAULT_WIDTH_MM); ++ input_abs_set_res(ts->pen_input_dev, ABS_Y, y_max / PANEL_DEFAULT_HEIGHT_MM); ++ + input_set_abs_params(ts->pen_input_dev, ABS_PRESSURE, 0, PEN_PRESSURE_MAX, 0, 0); + input_set_abs_params(ts->pen_input_dev, ABS_DISTANCE, 0, PEN_DISTANCE_MAX, 0, 0); + input_set_abs_params(ts->pen_input_dev, ABS_TILT_X, PEN_TILT_MIN, PEN_TILT_MAX, 0, 0); @@ -1518,11 +1526,11 @@ index 000000000000..63c584f681d7 + init_completion(&ts->dev_pm_suspend_completion); + ts->fw_debug = false; + -+#ifdef CONFIG_FACTORY_BUILD ++//#ifdef CONFIG_FACTORY_BUILD + ts->pen_input_dev_enable = 1; -+#else -+ ts->pen_input_dev_enable = 0; -+#endif ++//#else ++// ts->pen_input_dev_enable = 0; ++//#endif + +#if BOOT_UPDATE_FIRMWARE + nvt_fwu_wq = alloc_workqueue("nvt_fwu_wq", WQ_UNBOUND | WQ_MEM_RECLAIM, 1); @@ -1782,6 +1790,7 @@ index 000000000000..63c584f681d7 + + if (ts->pen_input_dev_enable) { + NVT_LOG("if enable pen,will close it"); ++ disable_pen_input_device(true); + } + + if (ts->db_wakeup) { @@ -1850,6 +1859,12 @@ index 000000000000..63c584f681d7 + if (ts->dev_pm_suspend) + pm_stay_awake(dev); + ++ // Xiaomi Pad 6 panel has some delay before turning on ++ if (ts->desc->input_calc_method == NVT_INPUT_CALC_NT36532) ++ { ++ msleep(750); ++ } ++ + mutex_lock(&ts->lock); + + NVT_LOG("resume start\n"); @@ -1879,6 +1894,7 @@ index 000000000000..63c584f681d7 + + mutex_unlock(&ts->lock); + ++ disable_pen_input_device(false); + if (likely(ts->ic_state == NVT_IC_RESUME_IN)) { + ts->ic_state = NVT_IC_RESUME_OUT; + } else { @@ -1955,16 +1971,33 @@ index 000000000000..63c584f681d7 +}; + +static const struct spi_device_id nvt_ts_id[] = { -+ { NVT_SPI_NAME, 0 }, ++ { "NVT-ts-spi", 0 }, ++ { "NVT-ts-spi-nt36532", 0 }, + { } +}; +MODULE_DEVICE_TABLE(spi, nvt_ts_id); + +#ifdef CONFIG_OF ++ ++static const struct nvt_ts_desc nt36523_desc = { ++ .mmap = &NT36523_memory_map, ++ .hw_crc = HWCRC_LEN_3Bytes, ++ .auto_copy = CHECK_SPI_DMA_TX_INFO, ++ .input_calc_method = NVT_INPUT_CALC_NT36523, ++}; ++static const struct nvt_ts_desc nt36532_desc = { ++ .mmap = &NT36532_cascade_memory_map, ++ .hw_crc = HWCRC_LEN_3Bytes, ++ .auto_copy = CHECK_TX_AUTO_COPY_EN, ++ .input_calc_method = NVT_INPUT_CALC_NT36532, ++}; ++ +static struct of_device_id nvt_match_table[] = { -+ { .compatible = "novatek,NVT-ts-spi",}, ++ { .compatible = "novatek,NVT-ts-spi", .data = &nt36523_desc }, ++ { .compatible = "novatek,NVT-ts-spi-nt36532", .data = &nt36532_desc }, + { }, +}; ++ +MODULE_DEVICE_TABLE(of, nvt_match_table); +#endif + @@ -1991,10 +2024,10 @@ index 000000000000..63c584f681d7 +MODULE_LICENSE("GPL"); diff --git a/drivers/input/touchscreen/nt36523/nt36xxx.h b/drivers/input/touchscreen/nt36523/nt36xxx.h new file mode 100644 -index 000000000000..6642ec2f26cf +index 000000000000..c826308a5492 --- /dev/null +++ b/drivers/input/touchscreen/nt36523/nt36xxx.h -@@ -0,0 +1,242 @@ +@@ -0,0 +1,261 @@ +/* + * Copyright (C) 2010 - 2018 Novatek, Inc. + * Copyright (C) 2021 XiaoMi, Inc. @@ -2067,7 +2100,9 @@ index 000000000000..6642ec2f26cf +#define PEN_DISTANCE_MAX (1) +#define PEN_TILT_MIN (-60) +#define PEN_TILT_MAX (60) -+ ++//---for pen resolution--- ++#define PANEL_DEFAULT_WIDTH_MM 148 // 148mm ++#define PANEL_DEFAULT_HEIGHT_MM 237 // 237mm +/* Enable only when module have tp reset pin and connected to host */ +#define NVT_TOUCH_SUPPORT_HW_RST 0 + @@ -2106,6 +2141,18 @@ index 000000000000..6642ec2f26cf + const char *nvt_limit_name; +}; + ++enum nvt_input_calc_method { ++ NVT_INPUT_CALC_NT36523, ++ NVT_INPUT_CALC_NT36532, ++}; ++ ++struct nvt_ts_desc { ++ const struct nvt_ts_mem_map *mmap; ++ uint8_t hw_crc; ++ uint8_t auto_copy; ++ enum nvt_input_calc_method input_calc_method; ++}; ++ +struct nvt_ts_data { + struct spi_device *client; + struct input_dev *input_dev; @@ -2125,16 +2172,18 @@ index 000000000000..6642ec2f26cf +#endif + uint32_t config_array_size; + struct nvt_config_info *config_array; ++ const struct nvt_ts_desc *desc; + const char *fw_name; + bool lkdown_readed; + uint8_t fw_ver; + uint8_t x_num; + uint8_t y_num; + int ic_state; -+ uint16_t abs_x_max; -+ uint16_t abs_y_max; ++ uint32_t abs_x_max; ++ uint32_t abs_y_max; + uint8_t max_touch_num; + uint8_t max_button_num; ++ uint8_t auto_copy; + uint32_t int_trigger_type; + int32_t irq_gpio; + uint32_t irq_flags; @@ -2226,12 +2275,15 @@ index 000000000000..6642ec2f26cf +int32_t nvt_clear_fw_status(void); +int32_t nvt_check_fw_status(void); +int32_t nvt_check_spi_dma_tx_info(void); ++int32_t nvt_check_tx_auto_copy(void); +int32_t nvt_set_page(uint32_t addr); +int32_t nvt_write_addr(uint32_t addr, uint8_t data); +int32_t nvt_read_pid(void); +bool nvt_get_dbgfw_status(void); +int32_t nvt_set_pocket_palm_switch(uint8_t pocket_palm_switch); +void Boot_Update_Firmware(struct work_struct *work); ++int32_t nvt_wait_auto_copy(void); ++int32_t disable_pen_input_device(bool disable); +#if NVT_TOUCH_ESD_PROTECT +extern void nvt_esd_check_enable(uint8_t enable); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ @@ -2239,16 +2291,15 @@ index 000000000000..6642ec2f26cf +#endif /* _LINUX_NVT_TOUCH_H */ diff --git a/drivers/input/touchscreen/nt36523/nt36xxx_fw_update.c b/drivers/input/touchscreen/nt36523/nt36xxx_fw_update.c new file mode 100644 -index 000000000000..4f383dac2c3c +index 000000000000..25e6b6f2da60 --- /dev/null +++ b/drivers/input/touchscreen/nt36523/nt36xxx_fw_update.c -@@ -0,0 +1,857 @@ +@@ -0,0 +1,902 @@ +/* -+ * Copyright (C) 2010 - 2018 Novatek, Inc. -+ * Copyright (C) 2021 XiaoMi, Inc. ++ * Copyright (C) 2010 - 2022 Novatek, Inc. + * -+ * $Revision: 68983 $ -+ * $Date: 2020-09-17 09:43:23 +0800 (週四, 17 九月 2020) $ ++ * $Revision: 77624 $ ++ * $Date: 2021-02-05 10:03:05 +0800 (週五, 05 二月 2021) $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by @@ -2268,14 +2319,12 @@ index 000000000000..4f383dac2c3c +#include "nt36xxx.h" + +#if BOOT_UPDATE_FIRMWARE -+ +#define SIZE_4KB 4096 ++#define NVT_FLASH_END_FLAG_LEN 3 +#define FLASH_SECTOR_SIZE SIZE_4KB +#define FW_BIN_VER_OFFSET (fw_need_write_size - SIZE_4KB) +#define FW_BIN_VER_BAR_OFFSET (FW_BIN_VER_OFFSET + 1) -+#define NVT_FLASH_END_FLAG_LEN 3 -+#define NVT_FLASH_END_FLAG_ADDR (fw_need_write_size - NVT_FLASH_END_FLAG_LEN) -+ ++#define DEFAULT_DEBUG_FW_NAME "novatek_debug_fw.bin" +static ktime_t start, end; +const struct firmware *fw_entry = NULL; +static size_t fw_need_write_size = 0; @@ -2291,6 +2340,35 @@ index 000000000000..4f383dac2c3c + +static struct nvt_ts_bin_map *bin_map; + ++static int32_t nvt_get_fw_need_write_size(const struct firmware *fw_entry) ++{ ++ int32_t i = 0; ++ int32_t total_sectors_to_check = 0; ++ ++ total_sectors_to_check = fw_entry->size / FLASH_SECTOR_SIZE; ++ /* printk("total_sectors_to_check = %d\n", total_sectors_to_check); */ ++ ++ for (i = total_sectors_to_check; i > 0; i--) { ++ /* printk("current end flag address checked = 0x%X\n", i * FLASH_SECTOR_SIZE - NVT_FLASH_END_FLAG_LEN); */ ++ /* check if there is end flag "NVT" at the end of this sector */ ++ if (strncmp(&fw_entry->data[i * FLASH_SECTOR_SIZE - NVT_FLASH_END_FLAG_LEN], "NVT", NVT_FLASH_END_FLAG_LEN) == 0) { ++ fw_need_write_size = i * FLASH_SECTOR_SIZE; ++ NVT_LOG("fw_need_write_size = %zu(0x%zx), NVT end flag\n", fw_need_write_size, fw_need_write_size); ++ return 0; ++ } ++ ++ /* check if there is end flag "MOD" at the end of this sector */ ++ if (strncmp(&fw_entry->data[i * FLASH_SECTOR_SIZE - NVT_FLASH_END_FLAG_LEN], "MOD", NVT_FLASH_END_FLAG_LEN) == 0) { ++ fw_need_write_size = i * FLASH_SECTOR_SIZE; ++ NVT_LOG("fw_need_write_size = %zu(0x%zx), MOD end flag\n", fw_need_write_size, fw_need_write_size); ++ return 0; ++ } ++ } ++ ++ NVT_ERR("end flag \"NVT\" \"MOD\" not found!\n"); ++ return -1; ++} ++ +/******************************************************* +Description: + Novatek touchscreen init variable and allocate buffer @@ -2552,7 +2630,12 @@ index 000000000000..4f383dac2c3c + goto request_fail; + } + -+ fw_need_write_size = fw_entry->size; ++ // check FW need to write size ++ if (nvt_get_fw_need_write_size(fw_entry)) { ++ NVT_ERR("get fw need to write size fail!\n"); ++ ret = -EINVAL; ++ goto invalid; ++ } + + // check if FW version add FW version bar equals 0xFF + if (*(fw_entry->data + FW_BIN_VER_OFFSET) + *(fw_entry->data + FW_BIN_VER_BAR_OFFSET) != 0xFF) { @@ -2769,10 +2852,10 @@ index 000000000000..4f383dac2c3c + fwbuf[0] = LENGTH_ADDR & 0x7F; + fwbuf[1] = (size) & 0xFF; + fwbuf[2] = (size >> 8) & 0xFF; -+ fwbuf[3] = (size >> 16) & 0x01; -+ if (ts->hw_crc == 1) { ++ fwbuf[3] = (size >> 16) & 0xFF; ++ if (ts->hw_crc == HWCRC_LEN_2Bytes) { + CTP_SPI_WRITE(ts->client, fwbuf, 3); -+ } else if (ts->hw_crc > 1) { ++ } else if (ts->hw_crc >= HWCRC_LEN_3Bytes) { + CTP_SPI_WRITE(ts->client, fwbuf, 4); + } + @@ -2912,9 +2995,9 @@ index 000000000000..4f383dac2c3c + goto fail; + } + -+ ret = nvt_check_spi_dma_tx_info(); ++ ret = nvt_wait_auto_copy(); + if (ret) { -+ NVT_ERR("spi dma tx info failed. (%d)\n", ret); ++ NVT_ERR("wait auto copy failed. (%d)\n", ret); + goto fail; + } + } else { @@ -2925,9 +3008,6 @@ index 000000000000..4f383dac2c3c + } + } + -+ /* enable hw bld crc function */ -+ nvt_bld_crc_enable(); -+ + /* clear fw reset status & enable fw crc check */ + nvt_fw_crc_enable(); + @@ -2971,6 +3051,9 @@ index 000000000000..4f383dac2c3c + + start = ktime_get(); + ++ NVT_LOG("Start firmware download\n"); ++ nvt_check_fw_reset_state(0x0A); ++ + while (1) { + /* + * Send eng reset cmd before download FW @@ -2987,6 +3070,9 @@ index 000000000000..4f383dac2c3c +#endif + nvt_bootloader_reset(); + ++ NVT_LOG("Reset bootloader\n"); ++ nvt_check_fw_reset_state(0x0A); ++ + /* clear fw reset status */ + nvt_write_addr(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_RESET_COMPLETE, 0x00); + @@ -2997,6 +3083,9 @@ index 000000000000..4f383dac2c3c + goto fail; + } + ++ NVT_LOG("Written firmware\n"); ++ nvt_check_fw_reset_state(0x0A); ++ + /* Set Boot Ready Bit */ + nvt_boot_ready(); + @@ -3095,17 +3184,25 @@ index 000000000000..4f383dac2c3c +void Boot_Update_Firmware(struct work_struct *work) +{ + mutex_lock(&ts->lock); -+ nvt_update_firmware(ts->fw_name); ++ if (nvt_get_dbgfw_status()) { ++ if (nvt_update_firmware(DEFAULT_DEBUG_FW_NAME) < 0) { ++ NVT_ERR("use built-in fw"); ++ nvt_update_firmware(ts->fw_name); ++ } ++ } else { ++ nvt_update_firmware(ts->fw_name); ++ } ++ disable_pen_input_device(false); + nvt_get_fw_info(); + mutex_unlock(&ts->lock); +} +#endif /* BOOT_UPDATE_FIRMWARE */ diff --git a/drivers/input/touchscreen/nt36523/nt36xxx_mem_map.h b/drivers/input/touchscreen/nt36523/nt36xxx_mem_map.h new file mode 100644 -index 000000000000..3f4195d636a0 +index 000000000000..b4b6fce51a60 --- /dev/null +++ b/drivers/input/touchscreen/nt36523/nt36xxx_mem_map.h -@@ -0,0 +1,390 @@ +@@ -0,0 +1,656 @@ +/* + * Copyright (C) 2010 - 2018 Novatek, Inc. + * Copyright (C) 2021 XiaoMi, Inc. @@ -3128,6 +3225,11 @@ index 000000000000..3f4195d636a0 +#define CHIP_VER_TRIM_ADDR 0x3F004 +#define CHIP_VER_TRIM_OLD_ADDR 0x1F64E + ++typedef struct nvt_ts_reg { ++ uint32_t addr; /* byte in which address */ ++ uint8_t mask; /* in which bits of that byte */ ++} nvt_ts_reg_t; ++ +struct nvt_ts_mem_map { + uint32_t EVENT_BUF_ADDR; + uint32_t RAW_PIPE0_ADDR; @@ -3156,8 +3258,14 @@ index 000000000000..3f4195d636a0 + uint32_t PEN_1D_DIFF_TIP_Y_ADDR; + uint32_t PEN_1D_DIFF_RING_X_ADDR; + uint32_t PEN_1D_DIFF_RING_Y_ADDR; ++ nvt_ts_reg_t ENB_CASC_REG; ++ /* FW History */ ++ uint32_t MMAP_HISTORY_EVENT0; ++ uint32_t MMAP_HISTORY_EVENT1; ++ /* START for flash FW update */ + uint32_t READ_FLASH_CHECKSUM_ADDR; + uint32_t RW_FLASH_DATA_ADDR; ++ /* END for FW Update Use */ + /* Phase 2 Host Download */ + uint32_t BOOT_RDY_ADDR; + uint32_t POR_CD_ADDR; @@ -3174,16 +3282,242 @@ index 000000000000..3f4195d636a0 + uint32_t G_DLM_CHECKSUM_ADDR; + uint32_t R_ILM_CHECKSUM_ADDR; + uint32_t R_DLM_CHECKSUM_ADDR; -+ uint32_t BLD_CRC_EN_ADDR; + uint32_t DMA_CRC_EN_ADDR; + uint32_t BLD_ILM_DLM_CRC_ADDR; + uint32_t DMA_CRC_FLAG_ADDR; -+ uint32_t FW_HISTORY_ADDR; +}; + +struct nvt_ts_hw_info { -+ uint8_t carrier_system; + uint8_t hw_crc; ++ uint8_t auto_copy; ++ bool use_gcm; ++ const struct nvt_ts_hw_reg_addr_info *hw_regs; ++}; ++ ++typedef enum { ++ HWCRC_NOSUPPORT = 0x00, ++ HWCRC_LEN_2Bytes = 0x01, ++ HWCRC_LEN_3Bytes = 0x02, ++} HWCRCBankConfig; ++ ++typedef enum { ++ AUTOCOPY_NOSUPPORT = 0x00, ++ CHECK_SPI_DMA_TX_INFO = 0x01, ++ CHECK_TX_AUTO_COPY_EN = 0x02, ++} AUTOCOPYCheck; ++ ++/* hw info reg*/ ++struct nvt_ts_hw_reg_addr_info { ++ uint32_t chip_ver_trim_addr; ++ uint32_t swrst_sif_addr; ++ uint32_t crc_err_flag_addr; ++}; ++ ++static const struct nvt_ts_hw_reg_addr_info hw_reg_addr_info = { ++ .chip_ver_trim_addr = 0x1FB104, ++ .swrst_sif_addr = 0x1FB43E, ++ .crc_err_flag_addr = 0x1FB535, ++}; ++ ++static const struct nvt_ts_hw_reg_addr_info hw_reg_addr_info_old_w_isp = { ++ .chip_ver_trim_addr = 0x3F004, ++ .swrst_sif_addr = 0x3F0FE, ++ .crc_err_flag_addr = 0x3F135, ++}; ++ ++static const struct nvt_ts_hw_reg_addr_info hw_reg_addr_info_legacy_w_isp = { ++ .chip_ver_trim_addr = 0x1F64E, ++ .swrst_sif_addr = 0x1F01A, ++ .crc_err_flag_addr = 0, ++}; ++ ++/* tddi */ ++static const struct nvt_ts_mem_map NT36532_cascade_memory_map = { ++ .EVENT_BUF_ADDR = 0x125800, ++ .RAW_PIPE0_ADDR = 0x10B200, ++ .RAW_PIPE1_ADDR = 0x10B200, ++ .BASELINE_ADDR = 0x109E00, ++ .BASELINE_BTN_ADDR = 0, ++ .DIFF_PIPE0_ADDR = 0x128140, ++ .DIFF_PIPE1_ADDR = 0x129540, ++ .RAW_BTN_PIPE0_ADDR = 0, ++ .RAW_BTN_PIPE1_ADDR = 0, ++ .DIFF_BTN_PIPE0_ADDR = 0, ++ .DIFF_BTN_PIPE1_ADDR = 0, ++ .PEN_2D_BL_TIP_X_ADDR = 0x10F940, ++ .PEN_2D_BL_TIP_Y_ADDR = 0x10FD40, ++ .PEN_2D_BL_RING_X_ADDR = 0x110140, ++ .PEN_2D_BL_RING_Y_ADDR = 0x110540, ++ .PEN_2D_DIFF_TIP_X_ADDR = 0x111140, ++ .PEN_2D_DIFF_TIP_Y_ADDR = 0x111540, ++ .PEN_2D_DIFF_RING_X_ADDR = 0x111940, ++ .PEN_2D_DIFF_RING_Y_ADDR = 0x111D40, ++ .PEN_2D_RAW_TIP_X_ADDR = 0x126E00, ++ .PEN_2D_RAW_TIP_Y_ADDR = 0x127210, ++ .PEN_2D_RAW_RING_X_ADDR = 0x127620, ++ .PEN_2D_RAW_RING_Y_ADDR = 0x127A30, ++ .PEN_1D_DIFF_TIP_X_ADDR = 0x127E40, ++ .PEN_1D_DIFF_TIP_Y_ADDR = 0x127EC0, ++ .PEN_1D_DIFF_RING_X_ADDR = 0x127F40, ++ .PEN_1D_DIFF_RING_Y_ADDR = 0x127FC0, ++ .ENB_CASC_REG = {.addr = 0x1FB12C, .mask = 0x01}, ++ /* FW History */ ++ .MMAP_HISTORY_EVENT0 = 0x121AFC, ++ .MMAP_HISTORY_EVENT1 = 0x121B3C, ++ /* Phase 2 Host Download */ ++ .BOOT_RDY_ADDR = 0x1FB50D, ++ .TX_AUTO_COPY_EN = 0x1FC925, ++ .SPI_DMA_TX_INFO = 0x1FC914, ++ /* BLD CRC */ ++ .BLD_LENGTH_ADDR = 0x1FB538, //0x1FB538 ~ 0x1FB53A (3 bytes) ++ .ILM_LENGTH_ADDR = 0x1FB518, //0x1FB518 ~ 0x1FB51A (3 bytes) ++ .DLM_LENGTH_ADDR = 0x1FB530, //0x1FB530 ~ 0x1FB532 (3 bytes) ++ .BLD_DES_ADDR = 0x1FB514, //0x1FB514 ~ 0x1FB516 (3 bytes) ++ .ILM_DES_ADDR = 0x1FB528, //0x1FB528 ~ 0x1FB52A (3 bytes) ++ .DLM_DES_ADDR = 0x1FB52C, //0x1FB52C ~ 0x1FB52E (3 bytes) ++ .G_ILM_CHECKSUM_ADDR = 0x1FB500, //0x1FB500 ~ 0x1FB503 (4 bytes) ++ .G_DLM_CHECKSUM_ADDR = 0x1FB504, //0x1FB504 ~ 0x1FB507 (4 bytes) ++ .R_ILM_CHECKSUM_ADDR = 0x1FB520, //0x1FB520 ~ 0x1FB523 (4 bytes) ++ .R_DLM_CHECKSUM_ADDR = 0x1FB524, //0x1FB524 ~ 0x1FB527 (4 bytes) ++ .DMA_CRC_EN_ADDR = 0x1FB536, ++ .BLD_ILM_DLM_CRC_ADDR = 0x1FB533, ++ .DMA_CRC_FLAG_ADDR = 0x1FB534, ++}; ++ ++static const struct nvt_ts_mem_map NT36532_single_memory_map = { ++ .EVENT_BUF_ADDR = 0x125800, ++ .RAW_PIPE0_ADDR = 0x10C1EC, ++ .RAW_PIPE1_ADDR = 0x10C1EC, ++ .BASELINE_ADDR = 0x10B1EC, ++ .BASELINE_BTN_ADDR = 0, ++ .DIFF_PIPE0_ADDR = 0x11BFC4, ++ .DIFF_PIPE1_ADDR = 0x11CFC4, ++ .RAW_BTN_PIPE0_ADDR = 0, ++ .RAW_BTN_PIPE1_ADDR = 0, ++ .DIFF_BTN_PIPE0_ADDR = 0, ++ .DIFF_BTN_PIPE1_ADDR = 0, ++ .PEN_2D_BL_TIP_X_ADDR = 0x11E5EC, ++ .PEN_2D_BL_TIP_Y_ADDR = 0x126C00, ++ .PEN_2D_BL_RING_X_ADDR = 0x11E7EC, ++ .PEN_2D_BL_RING_Y_ADDR = 0x126E00, ++ .PEN_2D_DIFF_TIP_X_ADDR = 0x11E1EC, ++ .PEN_2D_DIFF_TIP_Y_ADDR = 0x11E9EC, ++ .PEN_2D_DIFF_RING_X_ADDR = 0x11E3EC, ++ .PEN_2D_DIFF_RING_Y_ADDR = 0x11EBEC, ++ .PEN_2D_RAW_TIP_X_ADDR = 0x120CEC, ++ .PEN_2D_RAW_TIP_Y_ADDR = 0x120EFC, ++ .PEN_2D_RAW_RING_X_ADDR = 0x12110C, ++ .PEN_2D_RAW_RING_Y_ADDR = 0x12131C, ++ .PEN_1D_DIFF_TIP_X_ADDR = 0x126A00, ++ .PEN_1D_DIFF_TIP_Y_ADDR = 0x126A80, ++ .PEN_1D_DIFF_RING_X_ADDR = 0x126B00, ++ .PEN_1D_DIFF_RING_Y_ADDR = 0x126B80, ++ .ENB_CASC_REG = {.addr = 0x1FB12C, .mask = 0x01}, ++ /* FW History */ ++ .MMAP_HISTORY_EVENT0 = 0x122930, ++ .MMAP_HISTORY_EVENT1 = 0x122970, ++ /* Phase 2 Host Download */ ++ .BOOT_RDY_ADDR = 0x1FB50D, ++ .TX_AUTO_COPY_EN = 0x1FC925, ++ .SPI_DMA_TX_INFO = 0x1FC914, ++ /* BLD CRC */ ++ .BLD_LENGTH_ADDR = 0x1FB538, //0x1FB538 ~ 0x1FB53A (3 bytes) ++ .ILM_LENGTH_ADDR = 0x1FB518, //0x1FB518 ~ 0x1FB51A (3 bytes) ++ .DLM_LENGTH_ADDR = 0x1FB530, //0x1FB530 ~ 0x1FB532 (3 bytes) ++ .BLD_DES_ADDR = 0x1FB514, //0x1FB514 ~ 0x1FB516 (3 bytes) ++ .ILM_DES_ADDR = 0x1FB528, //0x1FB528 ~ 0x1FB52A (3 bytes) ++ .DLM_DES_ADDR = 0x1FB52C, //0x1FB52C ~ 0x1FB52E (3 bytes) ++ .G_ILM_CHECKSUM_ADDR = 0x1FB500, //0x1FB500 ~ 0x1FB503 (4 bytes) ++ .G_DLM_CHECKSUM_ADDR = 0x1FB504, //0x1FB504 ~ 0x1FB507 (4 bytes) ++ .R_ILM_CHECKSUM_ADDR = 0x1FB520, //0x1FB520 ~ 0x1FB523 (4 bytes) ++ .R_DLM_CHECKSUM_ADDR = 0x1FB524, //0x1FB524 ~ 0x1FB527 (4 bytes) ++ .DMA_CRC_EN_ADDR = 0x1FB536, ++ .BLD_ILM_DLM_CRC_ADDR = 0x1FB533, ++ .DMA_CRC_FLAG_ADDR = 0x1FB534, ++}; ++ ++static const struct nvt_ts_mem_map NT36523N_memory_map = { ++ .EVENT_BUF_ADDR = 0x2FD00, ++ .RAW_PIPE0_ADDR = 0x30FA0, ++ .RAW_PIPE1_ADDR = 0x30FA0, ++ .BASELINE_ADDR = 0x36510, ++ .BASELINE_BTN_ADDR = 0, ++ .DIFF_PIPE0_ADDR = 0x373E8, ++ .DIFF_PIPE1_ADDR = 0x38068, ++ .RAW_BTN_PIPE0_ADDR = 0, ++ .RAW_BTN_PIPE1_ADDR = 0, ++ .DIFF_BTN_PIPE0_ADDR = 0, ++ .DIFF_BTN_PIPE1_ADDR = 0, ++ .PEN_2D_BL_TIP_X_ADDR = 0x2988A, ++ .PEN_2D_BL_TIP_Y_ADDR = 0x29A1A, ++ .PEN_2D_BL_RING_X_ADDR = 0x29BAA, ++ .PEN_2D_BL_RING_Y_ADDR = 0x29D3A, ++ .PEN_2D_DIFF_TIP_X_ADDR = 0x29ECA, ++ .PEN_2D_DIFF_TIP_Y_ADDR = 0x2A05A, ++ .PEN_2D_DIFF_RING_X_ADDR = 0x2A1EA, ++ .PEN_2D_DIFF_RING_Y_ADDR = 0x2A37A, ++ .PEN_2D_RAW_TIP_X_ADDR = 0x2A50A, ++ .PEN_2D_RAW_TIP_Y_ADDR = 0x2A69A, ++ .PEN_2D_RAW_RING_X_ADDR = 0x2A82A, ++ .PEN_2D_RAW_RING_Y_ADDR = 0x2A9BA, ++ .PEN_1D_DIFF_TIP_X_ADDR = 0x2AB4A, ++ .PEN_1D_DIFF_TIP_Y_ADDR = 0x2ABAE, ++ .PEN_1D_DIFF_RING_X_ADDR = 0x2AC12, ++ .PEN_1D_DIFF_RING_Y_ADDR = 0x2AC76, ++ /* FW History */ ++ .MMAP_HISTORY_EVENT0 = 0x38D54, ++ .MMAP_HISTORY_EVENT1 = 0x38D94, ++ /* Phase 2 Host Download */ ++ .BOOT_RDY_ADDR = 0x3F10D, ++ .TX_AUTO_COPY_EN = 0x3F7E8, ++ .SPI_DMA_TX_INFO = 0x3F7F1, ++ /* BLD CRC */ ++ .BLD_LENGTH_ADDR = 0x3F138, //0x3F138 ~ 0x3F13A (3 bytes) ++ .ILM_LENGTH_ADDR = 0x3F118, //0x3F118 ~ 0x3F11A (3 bytes) ++ .DLM_LENGTH_ADDR = 0x3F130, //0x3F130 ~ 0x3F132 (3 bytes) ++ .BLD_DES_ADDR = 0x3F114, //0x3F114 ~ 0x3F116 (3 bytes) ++ .ILM_DES_ADDR = 0x3F128, //0x3F128 ~ 0x3F12A (3 bytes) ++ .DLM_DES_ADDR = 0x3F12C, //0x3F12C ~ 0x3F12E (3 bytes) ++ .G_ILM_CHECKSUM_ADDR = 0x3F100, //0x3F100 ~ 0x3F103 (4 bytes) ++ .G_DLM_CHECKSUM_ADDR = 0x3F104, //0x3F104 ~ 0x3F107 (4 bytes) ++ .R_ILM_CHECKSUM_ADDR = 0x3F120, //0x3F120 ~ 0x3F123 (4 bytes) ++ .R_DLM_CHECKSUM_ADDR = 0x3F124, //0x3F124 ~ 0x3F127 (4 bytes) ++ .DMA_CRC_EN_ADDR = 0x3F136, ++ .BLD_ILM_DLM_CRC_ADDR = 0x3F133, ++ .DMA_CRC_FLAG_ADDR = 0x3F134, ++}; ++ ++static const struct nvt_ts_mem_map NT36528_memory_map = { ++ .EVENT_BUF_ADDR = 0x22D00, ++ .RAW_PIPE0_ADDR = 0x24000, ++ .RAW_PIPE1_ADDR = 0x24000, ++ .BASELINE_ADDR = 0x21880, ++ .BASELINE_BTN_ADDR = 0, ++ .DIFF_PIPE0_ADDR = 0x20B00, ++ .DIFF_PIPE1_ADDR = 0x24B00, ++ .RAW_BTN_PIPE0_ADDR = 0, ++ .RAW_BTN_PIPE1_ADDR = 0, ++ .DIFF_BTN_PIPE0_ADDR = 0, ++ .DIFF_BTN_PIPE1_ADDR = 0, ++ /* FW History */ ++ .MMAP_HISTORY_EVENT0 = 0x23768, ++ .MMAP_HISTORY_EVENT1 = 0x237A8, ++ /* Phase 2 Host Download */ ++ .BOOT_RDY_ADDR = 0x3F10D, ++ /* BLD CRC */ ++ .BLD_LENGTH_ADDR = 0x3F138, //0x3F138 ~ 0x3F13A (3 bytes) ++ .ILM_LENGTH_ADDR = 0x3F118, //0x3F118 ~ 0x3F11A (3 bytes) ++ .DLM_LENGTH_ADDR = 0x3F130, //0x3F130 ~ 0x3F132 (3 bytes) ++ .BLD_DES_ADDR = 0x3F114, //0x3F114 ~ 0x3F116 (3 bytes) ++ .ILM_DES_ADDR = 0x3F128, //0x3F128 ~ 0x3F12A (3 bytes) ++ .DLM_DES_ADDR = 0x3F12C, //0x3F12C ~ 0x3F12E (3 bytes) ++ .G_ILM_CHECKSUM_ADDR = 0x3F100, //0x3F100 ~ 0x3F103 (4 bytes) ++ .G_DLM_CHECKSUM_ADDR = 0x3F104, //0x3F104 ~ 0x3F107 (4 bytes) ++ .R_ILM_CHECKSUM_ADDR = 0x3F120, //0x3F120 ~ 0x3F123 (4 bytes) ++ .R_DLM_CHECKSUM_ADDR = 0x3F124, //0x3F124 ~ 0x3F127 (4 bytes) ++ .DMA_CRC_EN_ADDR = 0x3F136, ++ .BLD_ILM_DLM_CRC_ADDR = 0x3F133, ++ .DMA_CRC_FLAG_ADDR = 0x3F134, +}; + +static const struct nvt_ts_mem_map NT36523_memory_map = { @@ -3214,8 +3548,9 @@ index 000000000000..3f4195d636a0 + .PEN_1D_DIFF_TIP_Y_ADDR = 0x2ABAE, + .PEN_1D_DIFF_RING_X_ADDR = 0x2AC12, + .PEN_1D_DIFF_RING_Y_ADDR = 0x2AC76, -+ .READ_FLASH_CHECKSUM_ADDR = 0x24000, -+ .RW_FLASH_DATA_ADDR = 0x24002, ++ /* FW History */ ++ .MMAP_HISTORY_EVENT0 = 0x38D54, ++ .MMAP_HISTORY_EVENT1 = 0x38D94, + /* Phase 2 Host Download */ + .BOOT_RDY_ADDR = 0x3F10D, + .TX_AUTO_COPY_EN = 0x3F7E8, @@ -3231,11 +3566,9 @@ index 000000000000..3f4195d636a0 + .G_DLM_CHECKSUM_ADDR = 0x3F104, //0x3F104 ~ 0x3F107 (4 bytes) + .R_ILM_CHECKSUM_ADDR = 0x3F120, //0x3F120 ~ 0x3F123 (4 bytes) + .R_DLM_CHECKSUM_ADDR = 0x3F124, //0x3F124 ~ 0x3F127 (4 bytes) -+ .BLD_CRC_EN_ADDR = 0x3F30E, + .DMA_CRC_EN_ADDR = 0x3F136, + .BLD_ILM_DLM_CRC_ADDR = 0x3F133, + .DMA_CRC_FLAG_ADDR = 0x3F134, -+ .FW_HISTORY_ADDR = 0x38D54, +}; + +static const struct nvt_ts_mem_map NT36526_memory_map = { @@ -3250,8 +3583,9 @@ index 000000000000..3f4195d636a0 + .RAW_BTN_PIPE1_ADDR = 0, + .DIFF_BTN_PIPE0_ADDR = 0, + .DIFF_BTN_PIPE1_ADDR = 0, -+ .READ_FLASH_CHECKSUM_ADDR = 0x24000, -+ .RW_FLASH_DATA_ADDR = 0x24002, ++ /* FW History */ ++ .MMAP_HISTORY_EVENT0 = 0x23C38, ++ .MMAP_HISTORY_EVENT1 = 0x23C78, + /* Phase 2 Host Download */ + .BOOT_RDY_ADDR = 0x3F10D, + /* BLD CRC */ @@ -3265,7 +3599,6 @@ index 000000000000..3f4195d636a0 + .G_DLM_CHECKSUM_ADDR = 0x3F104, //0x3F104 ~ 0x3F107 (4 bytes) + .R_ILM_CHECKSUM_ADDR = 0x3F120, //0x3F120 ~ 0x3F123 (4 bytes) + .R_DLM_CHECKSUM_ADDR = 0x3F124, //0x3F124 ~ 0x3F127 (4 bytes) -+ .BLD_CRC_EN_ADDR = 0x3F30E, + .DMA_CRC_EN_ADDR = 0x3F136, + .BLD_ILM_DLM_CRC_ADDR = 0x3F133, + .DMA_CRC_FLAG_ADDR = 0x3F134, @@ -3284,8 +3617,9 @@ index 000000000000..3f4195d636a0 + .RAW_BTN_PIPE1_ADDR = 0, + .DIFF_BTN_PIPE0_ADDR = 0, + .DIFF_BTN_PIPE1_ADDR = 0, -+ .READ_FLASH_CHECKSUM_ADDR = 0x24000, -+ .RW_FLASH_DATA_ADDR = 0x24002, ++ /* FW History */ ++ .MMAP_HISTORY_EVENT0 = 0x23D10, ++ .MMAP_HISTORY_EVENT1 = 0x23D50, + /* Phase 2 Host Download */ + .BOOT_RDY_ADDR = 0x3F10D, + /* BLD CRC */ @@ -3299,13 +3633,11 @@ index 000000000000..3f4195d636a0 + .G_DLM_CHECKSUM_ADDR = 0x3F104, //0x3F104 ~ 0x3F107 (4 bytes) + .R_ILM_CHECKSUM_ADDR = 0x3F120, //0x3F120 ~ 0x3F123 (4 bytes) + .R_DLM_CHECKSUM_ADDR = 0x3F124, //0x3F124 ~ 0x3F127 (4 bytes) -+ .BLD_CRC_EN_ADDR = 0x3F30E, + .DMA_CRC_EN_ADDR = 0x3F136, + .BLD_ILM_DLM_CRC_ADDR = 0x3F133, + .DMA_CRC_FLAG_ADDR = 0x3F134, +}; + -+ +static const struct nvt_ts_mem_map NT36672A_memory_map = { + .EVENT_BUF_ADDR = 0x21C00, + .RAW_PIPE0_ADDR = 0x20000, @@ -3318,8 +3650,9 @@ index 000000000000..3f4195d636a0 + .RAW_BTN_PIPE1_ADDR = 0x23510, + .DIFF_BTN_PIPE0_ADDR = 0x20BF0, + .DIFF_BTN_PIPE1_ADDR = 0x23BF0, -+ .READ_FLASH_CHECKSUM_ADDR = 0x24000, -+ .RW_FLASH_DATA_ADDR = 0x24002, ++ /* FW History */ ++ .MMAP_HISTORY_EVENT0 = 0x218D6, ++ .MMAP_HISTORY_EVENT1 = 0x24B2D, + /* Phase 2 Host Download */ + .BOOT_RDY_ADDR = 0x3F10D, + /* BLD CRC */ @@ -3333,7 +3666,6 @@ index 000000000000..3f4195d636a0 + .G_DLM_CHECKSUM_ADDR = 0x3F104, //0x3F104 ~ 0x3F107 (4 bytes) + .R_ILM_CHECKSUM_ADDR = 0x3F120, //0x3F120 ~ 0x3F123 (4 bytes) + .R_DLM_CHECKSUM_ADDR = 0x3F124, //0x3F124 ~ 0x3F127 (4 bytes) -+ .BLD_CRC_EN_ADDR = 0x3F30E, + .DMA_CRC_EN_ADDR = 0x3F132, + .BLD_ILM_DLM_CRC_ADDR = 0x3F133, + .DMA_CRC_FLAG_ADDR = 0x3F134, @@ -3351,8 +3683,9 @@ index 000000000000..3f4195d636a0 + .RAW_BTN_PIPE1_ADDR = 0x12E60, + .DIFF_BTN_PIPE0_ADDR = 0x10E68, + .DIFF_BTN_PIPE1_ADDR = 0x12E68, -+ .READ_FLASH_CHECKSUM_ADDR = 0x14000, -+ .RW_FLASH_DATA_ADDR = 0x14002, ++ /* FW History */ ++ .MMAP_HISTORY_EVENT0 = 0, ++ .MMAP_HISTORY_EVENT1 = 0, + /* Phase 2 Host Download */ + .BOOT_RDY_ADDR = 0x1F141, + .POR_CD_ADDR = 0x1F61C, @@ -3372,8 +3705,9 @@ index 000000000000..3f4195d636a0 + .RAW_BTN_PIPE1_ADDR = 0x12634, + .DIFF_BTN_PIPE0_ADDR = 0x10AFC, + .DIFF_BTN_PIPE1_ADDR = 0x12AFC, -+ .READ_FLASH_CHECKSUM_ADDR = 0x14000, -+ .RW_FLASH_DATA_ADDR = 0x14002, ++ /* FW History */ ++ .MMAP_HISTORY_EVENT0 = 0, ++ .MMAP_HISTORY_EVENT1 = 0, + /* Phase 2 Host Download */ + .BOOT_RDY_ADDR = 0x1F141, + .POR_CD_ADDR = 0x1F61C, @@ -3393,43 +3727,69 @@ index 000000000000..3f4195d636a0 + .RAW_BTN_PIPE1_ADDR = 0x12634, + .DIFF_BTN_PIPE0_ADDR = 0x10AFC, + .DIFF_BTN_PIPE1_ADDR = 0x12AFC, -+ .READ_FLASH_CHECKSUM_ADDR = 0x14000, -+ .RW_FLASH_DATA_ADDR = 0x14002, ++ /* FW History */ ++ .MMAP_HISTORY_EVENT0 = 0, ++ .MMAP_HISTORY_EVENT1 = 0, ++ /* Phase 2 Host Download */ ++ .BOOT_RDY_ADDR = 0x1F141, ++ .POR_CD_ADDR = 0x1F61C, ++ /* BLD CRC */ ++ .R_ILM_CHECKSUM_ADDR = 0x1BF00, ++}; ++ ++static struct nvt_ts_hw_info NT36532_hw_info = { ++ .hw_crc = HWCRC_LEN_3Bytes, ++ .auto_copy = CHECK_TX_AUTO_COPY_EN, ++ .use_gcm = 1, ++ .hw_regs = &hw_reg_addr_info, ++}; ++ ++static struct nvt_ts_hw_info NT36528_hw_info = { ++ .hw_crc = HWCRC_LEN_3Bytes, ++ .auto_copy = AUTOCOPY_NOSUPPORT, ++ .hw_regs = &hw_reg_addr_info_old_w_isp, +}; + +static struct nvt_ts_hw_info NT36523_hw_info = { -+ .carrier_system = 2, -+ .hw_crc = 2, ++ .hw_crc = HWCRC_LEN_3Bytes, ++ .auto_copy = CHECK_SPI_DMA_TX_INFO, ++ .hw_regs = &hw_reg_addr_info_old_w_isp, +}; + +static struct nvt_ts_hw_info NT36526_hw_info = { -+ .carrier_system = 2, -+ .hw_crc = 2, ++ .hw_crc = HWCRC_LEN_3Bytes, ++ .auto_copy = AUTOCOPY_NOSUPPORT, ++ .hw_regs = &hw_reg_addr_info_old_w_isp, +}; + +static struct nvt_ts_hw_info NT36675_hw_info = { -+ .carrier_system = 2, -+ .hw_crc = 2, ++ .hw_crc = HWCRC_LEN_3Bytes, ++ .auto_copy = AUTOCOPY_NOSUPPORT, ++ .hw_regs = &hw_reg_addr_info_old_w_isp, +}; + +static struct nvt_ts_hw_info NT36672A_hw_info = { -+ .carrier_system = 0, -+ .hw_crc = 1, ++ .hw_crc = HWCRC_LEN_2Bytes, ++ .auto_copy = AUTOCOPY_NOSUPPORT, ++ .hw_regs = &hw_reg_addr_info_old_w_isp, +}; + +static struct nvt_ts_hw_info NT36772_hw_info = { -+ .carrier_system = 0, -+ .hw_crc = 0, ++ .hw_crc = HWCRC_NOSUPPORT, ++ .auto_copy = AUTOCOPY_NOSUPPORT, ++ .hw_regs = &hw_reg_addr_info_legacy_w_isp, +}; + +static struct nvt_ts_hw_info NT36525_hw_info = { -+ .carrier_system = 0, -+ .hw_crc = 0, ++ .hw_crc = HWCRC_NOSUPPORT, ++ .auto_copy = AUTOCOPY_NOSUPPORT, ++ .hw_regs = &hw_reg_addr_info_legacy_w_isp, +}; + +static struct nvt_ts_hw_info NT36676F_hw_info = { -+ .carrier_system = 0, -+ .hw_crc = 0, ++ .hw_crc = HWCRC_NOSUPPORT, ++ .auto_copy = AUTOCOPY_NOSUPPORT, ++ .hw_regs = &hw_reg_addr_info_legacy_w_isp, +}; + +#define NVT_ID_BYTE_MAX 6 @@ -3437,10 +3797,13 @@ index 000000000000..3f4195d636a0 + uint8_t id[NVT_ID_BYTE_MAX]; + uint8_t mask[NVT_ID_BYTE_MAX]; + const struct nvt_ts_mem_map *mmap; ++ const struct nvt_ts_mem_map *mmap_casc; + const struct nvt_ts_hw_info *hwinfo; +}; + +static const struct nvt_ts_trim_id_table trim_id_table[] = { ++ {.id = {0xFF, 0xFF, 0xFF, 0x32, 0x65, 0x03}, .mask = {0, 0, 0, 1, 1, 1}, ++ .mmap = &NT36532_single_memory_map, .mmap_casc = &NT36532_cascade_memory_map, .hwinfo = &NT36532_hw_info}, + {.id = {0x20, 0xFF, 0xFF, 0x23, 0x65, 0x03}, .mask = {1, 0, 0, 1, 1, 1}, + .mmap = &NT36523_memory_map, .hwinfo = &NT36523_hw_info}, + {.id = {0x0C, 0xFF, 0xFF, 0x23, 0x65, 0x03}, .mask = {1, 0, 0, 1, 1, 1}, diff --git a/device/testing/linux-xiaomi-pipa/0005-drm-Add-drm-notifier-support.patch b/device/testing/linux-xiaomi-pipa/0005-drm-Add-drm-notifier-support.patch index 754d52d5c..94426c996 100644 --- a/device/testing/linux-xiaomi-pipa/0005-drm-Add-drm-notifier-support.patch +++ b/device/testing/linux-xiaomi-pipa/0005-drm-Add-drm-notifier-support.patch @@ -1,4 +1,4 @@ -From 52a2cbde53677a53453b512558f3cb2213fd87bc Mon Sep 17 00:00:00 2001 +From bf99cf395af1bccc191828aba631ca18fa4ecbc1 Mon Sep 17 00:00:00 2001 From: Jianhua Lu Date: Thu, 4 Aug 2022 13:26:53 +0800 Subject: [PATCH 05/12] drm: Add drm notifier support diff --git a/device/testing/linux-xiaomi-pipa/0006-drm-dsi-emit-panel-turn-on-off-signal-to-touchscreen.patch b/device/testing/linux-xiaomi-pipa/0006-drm-dsi-emit-panel-turn-on-off-signal-to-touchscreen.patch index 5b556185e..c4fad215d 100644 --- a/device/testing/linux-xiaomi-pipa/0006-drm-dsi-emit-panel-turn-on-off-signal-to-touchscreen.patch +++ b/device/testing/linux-xiaomi-pipa/0006-drm-dsi-emit-panel-turn-on-off-signal-to-touchscreen.patch @@ -1,4 +1,4 @@ -From 34f033b66626bf82954f17a09ba3877ace034f2a Mon Sep 17 00:00:00 2001 +From 124895bab4804060519eb52dad4dbc9178d2c62f Mon Sep 17 00:00:00 2001 From: Jianhua Lu Date: Mon, 17 Oct 2022 08:02:58 +0800 Subject: [PATCH 06/12] drm: dsi: emit panel turn on/off signal to touchscreen diff --git a/device/testing/linux-xiaomi-pipa/0007-drm-msm-dsi-change-sync-mode-to-sync-on-DSI0-rather-.patch b/device/testing/linux-xiaomi-pipa/0007-drm-msm-dsi-change-sync-mode-to-sync-on-DSI0-rather-.patch index 451ae43a6..72500a3f4 100644 --- a/device/testing/linux-xiaomi-pipa/0007-drm-msm-dsi-change-sync-mode-to-sync-on-DSI0-rather-.patch +++ b/device/testing/linux-xiaomi-pipa/0007-drm-msm-dsi-change-sync-mode-to-sync-on-DSI0-rather-.patch @@ -1,4 +1,4 @@ -From 1afc0d0edec9d42ba072af2fe07380154186d55f Mon Sep 17 00:00:00 2001 +From 73515e9b78e92abfca144f95ef9ce2f44a88e83a Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 4 Jun 2023 21:44:33 +0300 Subject: [PATCH 07/12] drm/msm/dsi: change sync mode to sync on DSI0 rather diff --git a/device/testing/linux-xiaomi-pipa/0008-drm-msm-dsi-support-DSC-configurations-with-slice_pe.patch b/device/testing/linux-xiaomi-pipa/0008-drm-msm-dsi-support-DSC-configurations-with-slice_pe.patch index 8d319d8a0..aabb260db 100644 --- a/device/testing/linux-xiaomi-pipa/0008-drm-msm-dsi-support-DSC-configurations-with-slice_pe.patch +++ b/device/testing/linux-xiaomi-pipa/0008-drm-msm-dsi-support-DSC-configurations-with-slice_pe.patch @@ -1,4 +1,4 @@ -From c6a632815c2f558bf8f8b29a17df05f5a914eecd Mon Sep 17 00:00:00 2001 +From 4fdf0e7715ba08b393fb80fac427f44d02b71374 Mon Sep 17 00:00:00 2001 From: Jun Nie Date: Wed, 1 Oct 2025 21:59:13 +0800 Subject: [PATCH 08/12] drm/msm/dsi: support DSC configurations with @@ -19,7 +19,7 @@ Signed-off-by: Junjie Cao 2 files changed, 12 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c -index e0de545d4077..773ce8520698 100644 +index db6da99375a1..519410ec5197 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -166,6 +166,7 @@ struct msm_dsi_host { @@ -30,7 +30,7 @@ index e0de545d4077..773ce8520698 100644 /* connected device info */ unsigned int channel; -@@ -910,17 +911,10 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod +@@ -927,17 +928,10 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod slice_per_intf = dsc->slice_count; total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf; @@ -50,7 +50,7 @@ index e0de545d4077..773ce8520698 100644 if (is_cmd_mode) /* packet data type */ reg = DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE); -@@ -1069,12 +1063,8 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) +@@ -1088,12 +1082,8 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) else /* * When DSC is enabled, WC = slice_chunk_size * slice_per_pkt + 1. @@ -64,7 +64,7 @@ index e0de545d4077..773ce8520698 100644 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL, DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) | -@@ -1683,8 +1673,13 @@ static int dsi_host_attach(struct mipi_dsi_host *host, +@@ -1702,8 +1692,13 @@ static int dsi_host_attach(struct mipi_dsi_host *host, msm_host->lanes = dsi->lanes; msm_host->format = dsi->format; msm_host->mode_flags = dsi->mode_flags; diff --git a/device/testing/linux-xiaomi-pipa/0009-drm-panel-Add-support-for-Novatek-NT36532-panel.patch b/device/testing/linux-xiaomi-pipa/0009-drm-panel-Add-support-for-Novatek-NT36532-panel.patch index 656aa3e20..08dc0f4b3 100644 --- a/device/testing/linux-xiaomi-pipa/0009-drm-panel-Add-support-for-Novatek-NT36532-panel.patch +++ b/device/testing/linux-xiaomi-pipa/0009-drm-panel-Add-support-for-Novatek-NT36532-panel.patch @@ -1,4 +1,4 @@ -From cd970caef6ef84c7d6926227e6b655976dfa2928 Mon Sep 17 00:00:00 2001 +From 345977da9c305bcdd89298df96ad178f5f8b0927 Mon Sep 17 00:00:00 2001 From: Arseniy Velikanov Date: Wed, 11 Feb 2026 21:05:40 +0700 Subject: [PATCH 09/12] drm/panel: Add support for Novatek NT36532 panel @@ -8,21 +8,11 @@ including support for the CSOT panel used in the Xiaomi Pad 6 tablets. Co-developed-by: Ryo Kenrie Wongso Signed-off-by: Ryo Kenrie Wongso - -input: nt36xxx: Enable pen support - -nt36xxx: add pen input resolution - -input/touchscreen: nt36523: add support for pipa in driver --- drivers/gpu/drm/panel/Kconfig | 10 + drivers/gpu/drm/panel/Makefile | 1 + drivers/gpu/drm/panel/panel-novatek-nt36532.c | 609 ++++++++++++++++++ - drivers/input/touchscreen/nt36523/nt36xxx.c | 331 +++++----- - drivers/input/touchscreen/nt36523/nt36xxx.h | 25 +- - .../touchscreen/nt36523/nt36xxx_fw_update.c | 81 ++- - .../touchscreen/nt36523/nt36xxx_mem_map.h | 340 ++++++++-- - 7 files changed, 1190 insertions(+), 207 deletions(-) + 3 files changed, 620 insertions(+) create mode 100644 drivers/gpu/drm/panel/panel-novatek-nt36532.c diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig @@ -673,1215 +663,6 @@ index 000000000000..cf0c92766f89 +MODULE_AUTHOR("Luka Panio "); +MODULE_DESCRIPTION("DRM panel driver for the Novatek NT36532 Driver-IC"); +MODULE_LICENSE("GPL"); -diff --git a/drivers/input/touchscreen/nt36523/nt36xxx.c b/drivers/input/touchscreen/nt36523/nt36xxx.c -index 63c584f681d7..fc9829a6b6e0 100644 ---- a/drivers/input/touchscreen/nt36523/nt36xxx.c -+++ b/drivers/input/touchscreen/nt36523/nt36xxx.c -@@ -240,30 +240,6 @@ int32_t nvt_write_addr(uint32_t addr, uint8_t data) - return ret; - } - --/******************************************************* --Description: -- Novatek touchscreen enable hw bld crc function. -- --return: -- N/A. --*******************************************************/ --void nvt_bld_crc_enable(void) --{ -- uint8_t buf[4] = {0}; -- -- //---set xdata index to BLD_CRC_EN_ADDR--- -- nvt_set_page(ts->mmap->BLD_CRC_EN_ADDR); -- -- //---read data from index--- -- buf[0] = ts->mmap->BLD_CRC_EN_ADDR & (0x7F); -- buf[1] = 0xFF; -- CTP_SPI_READ(ts->client, buf, 2); -- -- //---write data to index--- -- buf[0] = ts->mmap->BLD_CRC_EN_ADDR & (0x7F); -- buf[1] = buf[1] | (0x01 << 7); -- CTP_SPI_WRITE(ts->client, buf, 2); --} - - /******************************************************* - Description: -@@ -322,10 +298,15 @@ void nvt_boot_ready(void) - *******************************************************/ - void nvt_tx_auto_copy_mode(void) - { -- //---write TX_AUTO_COPY_EN cmds--- -- nvt_write_addr(ts->mmap->TX_AUTO_COPY_EN, 0x69); -+ if (ts->auto_copy == CHECK_SPI_DMA_TX_INFO) { -+ //---write TX_AUTO_COPY_EN cmds--- -+ nvt_write_addr(ts->mmap->TX_AUTO_COPY_EN, 0x69); -+ } else if (ts->auto_copy == CHECK_TX_AUTO_COPY_EN) { -+ //---write SPI_MST_AUTO_COPY cmds--- -+ nvt_write_addr(ts->mmap->TX_AUTO_COPY_EN, 0x56); -+ } - -- NVT_ERR("tx auto copy mode enable\n"); -+ NVT_ERR("tx auto copy mode %d enable\n", ts->auto_copy); - } - - /******************************************************* -@@ -607,8 +588,6 @@ int32_t nvt_get_fw_info(void) - ts->fw_ver = buf[1]; - ts->x_num = buf[3]; - ts->y_num = buf[4]; -- ts->abs_x_max = (uint16_t)((buf[5] << 8) | buf[6]); -- ts->abs_y_max = (uint16_t)((buf[7] << 8) | buf[8]); - ts->max_button_num = buf[11]; - ts->cascade = buf[34] & 0x01; - if (ts->pen_support) { -@@ -622,8 +601,6 @@ int32_t nvt_get_fw_info(void) - ts->fw_ver = 0; - ts->x_num = 18; - ts->y_num = 32; -- ts->abs_x_max = TOUCH_DEFAULT_MAX_WIDTH; -- ts->abs_y_max = TOUCH_DEFAULT_MAX_HEIGHT; - ts->max_button_num = TOUCH_KEY_NUM; - - if(retry_count < 3) { -@@ -722,6 +699,25 @@ static int32_t nvt_parse_dt(struct device *dev) - NVT_LOG("spi-max-frequency: %u\n", ts->spi_max_freq); - } - -+ ret = of_property_read_u32(np, "touchscreen-size-x", &ts->abs_x_max); -+ if (ret || ts->abs_x_max == 0) { -+ NVT_LOG("Unable to get screen width\n"); -+ ts->abs_x_max = TOUCH_DEFAULT_MAX_WIDTH; -+ ret = 0; -+ } -+ -+ ret = of_property_read_u32(np, "touchscreen-size-y", &ts->abs_y_max); -+ if (ret || ts->abs_y_max == 0) { -+ NVT_LOG("Unable to get screen height\n"); -+ ts->abs_y_max = TOUCH_DEFAULT_MAX_HEIGHT; -+ ret = 0; -+ } -+ -+ ts->desc = of_device_get_match_data(dev); -+ if (!ts->desc) -+ return -ENODEV; -+ NVT_LOG("Detected input calc type %d\n", ts->desc->input_calc_method); -+ - return ret; - } - #else -@@ -853,76 +849,8 @@ static void nvt_esd_check_func(struct work_struct *work) - } - #endif /* #if NVT_TOUCH_ESD_PROTECT */ - --#if NVT_TOUCH_WDT_RECOVERY --static uint8_t recovery_cnt = 0; --static uint8_t nvt_wdt_fw_recovery(uint8_t *point_data) --{ -- uint32_t recovery_cnt_max = 10; -- uint8_t recovery_enable = false; -- uint8_t i = 0; -- -- recovery_cnt++; -- -- /* check pattern */ -- for (i=1 ; i<7 ; i++) { -- if ((point_data[i] != 0xFD) && (point_data[i] != 0xFE)) { -- recovery_cnt = 0; -- break; -- } -- } -- -- if (recovery_cnt > recovery_cnt_max){ -- recovery_enable = true; -- recovery_cnt = 0; -- } -- -- return recovery_enable; --} --#endif /* #if NVT_TOUCH_WDT_RECOVERY */ -- - #define PEN_DATA_LEN 14 - #define FW_HISTORY_SIZE 128 --static uint32_t nvt_dump_fw_history(void) --{ -- int32_t ret = 0; -- uint8_t buf[FW_HISTORY_SIZE + 1 + DUMMY_BYTES] = {0}; -- int32_t i = 0; -- char *tmp_dump = NULL; -- int32_t line_cnt = 0; -- -- if (ts->mmap->FW_HISTORY_ADDR == 0) { -- NVT_ERR("FW_HISTORY_ADDR not available!\n"); -- ret = -1; -- goto exit_nvt_dump_fw_history; -- } -- nvt_set_page(ts->mmap->FW_HISTORY_ADDR); -- buf[0] = ts->mmap->FW_HISTORY_ADDR & 0xFF; -- CTP_SPI_READ(ts->client, buf, FW_HISTORY_SIZE + 1); -- if (ret) { -- NVT_ERR("CTP_SPI_READ failed.(%d)\n", ret); -- ret = -1; -- goto exit_nvt_dump_fw_history; -- } -- -- tmp_dump = (char *)kzalloc(FW_HISTORY_SIZE * 4, GFP_KERNEL); -- for (i = 0; i < FW_HISTORY_SIZE; i++) { -- sprintf(tmp_dump + i * 3 + line_cnt, "%02X ", buf[1 + i]); -- if ((i + 1) % 16 == 0) { -- sprintf(tmp_dump + i * 3 + line_cnt + 3, "%c", '\n'); -- line_cnt++; -- } -- } -- NVT_LOG("%s", tmp_dump); -- --exit_nvt_dump_fw_history: -- if (tmp_dump) { -- kfree(tmp_dump); -- tmp_dump = NULL; -- } -- nvt_set_page(ts->mmap->EVENT_BUF_ADDR); -- -- return ret; --} - - #define POINT_DATA_LEN 65 - /******************************************************* -@@ -977,26 +905,6 @@ static irqreturn_t nvt_ts_work_func(int irq, void *data) - goto XFER_ERROR; - } - -- /*--- dump SPI buf --- -- for (i = 0; i < 10; i++) { -- NVT_LOG("%02X %02X %02X %02X %02X %02X \n", -- point_data[1+i*6], point_data[2+i*6], point_data[3+i*6], point_data[4+i*6], point_data[5+i*6], point_data[6+i*6]); -- } -- */ -- --#if NVT_TOUCH_WDT_RECOVERY -- /* ESD protect by WDT */ -- if (nvt_wdt_fw_recovery(point_data)) { -- NVT_ERR("Recover for fw reset, %02X\n", point_data[1]); -- if (point_data[1] == 0xFD) { -- NVT_ERR("Dump FW history:\n"); -- nvt_dump_fw_history(); -- } -- nvt_update_firmware(ts->fw_name); -- goto XFER_ERROR; -- } --#endif /* #if NVT_TOUCH_WDT_RECOVERY */ -- - /* ESD protect by FW handshake */ - if (nvt_fw_recovery(point_data)) { - #if NVT_TOUCH_ESD_PROTECT -@@ -1018,25 +926,40 @@ static irqreturn_t nvt_ts_work_func(int irq, void *data) - /* update interrupt timer */ - irq_timer = jiffies; - #endif /* #if NVT_TOUCH_ESD_PROTECT */ -- input_x = (uint32_t)(point_data[position + 1] << 4) + (uint32_t) (point_data[position + 3] >> 4); -- input_y = (uint32_t)(point_data[position + 2] << 4) + (uint32_t) (point_data[position + 3] & 0x0F); -+ if (ts->desc->input_calc_method == NVT_INPUT_CALC_NT36532) -+ { -+ input_x = (uint32_t)(point_data[position + 1] << 8) + (uint32_t) (point_data[position + 2]); -+ input_y = (uint32_t)(point_data[position + 3] << 8) + (uint32_t) (point_data[position + 4]); -+ } -+ else -+ { -+ input_x = (uint32_t)(point_data[position + 1] << 4) + (uint32_t) (point_data[position + 3] >> 4); -+ input_y = (uint32_t)(point_data[position + 2] << 4) + (uint32_t) (point_data[position + 3] & 0x0F); -+ } - if ((input_x < 0) || (input_y < 0)) - continue; - if ((input_x > ts->abs_x_max) || (input_y > ts->abs_y_max)) - continue; -- input_w = (uint32_t)(point_data[position + 4]); -- if (input_w == 0) -- input_w = 1; -- if (i < 2) { -- input_p = (uint32_t)(point_data[position + 5]) + (uint32_t)(point_data[i + 63] << 8); -- if (input_p > TOUCH_FORCE_NUM) -- input_p = TOUCH_FORCE_NUM; -- } else { -- input_p = (uint32_t)(point_data[position + 5]); -+ if (ts->desc->input_calc_method == NVT_INPUT_CALC_NT36532) -+ { -+ input_w = (uint32_t)(point_data[position + 5]); -+ if (input_w == 0) -+ input_w = 1; -+ input_p = (uint32_t)(point_data[1 + 98 + i]); -+ } -+ else -+ { -+ input_w = (uint32_t)(point_data[position + 4]); -+ if (i < 2) { -+ input_p = (uint32_t)(point_data[position + 5]) + (uint32_t)(point_data[i + 63] << 8); -+ if (input_p > TOUCH_FORCE_NUM) -+ input_p = TOUCH_FORCE_NUM; -+ } else { -+ input_p = (uint32_t)(point_data[position + 5]); -+ } - } - if (input_p == 0) - input_p = 1; -- - #if MT_PROTOCOL_B - press_id[input_id - 1] = 1; - input_mt_slot(ts->input_dev, input_id - 1); -@@ -1166,13 +1089,95 @@ static irqreturn_t nvt_ts_work_func(int irq, void *data) - *******************************************************/ - static int8_t nvt_ts_check_chip_ver_trim(uint32_t chip_ver_trim_addr) - { -- -- ts->mmap = &NT36523_memory_map; -- ts->carrier_system = NT36523_hw_info.carrier_system; -- ts->hw_crc = NT36523_hw_info.hw_crc; -+ ts->mmap = ts->desc->mmap; -+ ts->hw_crc = ts->desc->hw_crc; -+ ts->auto_copy = ts->desc->auto_copy; - return 0; - } - -+int32_t nvt_check_tx_auto_copy(void) -+{ -+ uint8_t buf[8] = {0}; -+ int32_t i = 0; -+ const int32_t retry = 200; -+ -+ if (ts->mmap->TX_AUTO_COPY_EN == 0) { -+ NVT_ERR("error, TX_AUTO_COPY_EN = 0\n"); -+ return -1; -+ } -+ -+ for (i = 0; i < retry; i++) { -+ //---set xdata index to SPI_MST_AUTO_COPY--- -+ nvt_set_page(ts->mmap->TX_AUTO_COPY_EN); -+ -+ //---read auto copy status--- -+ buf[0] = ts->mmap->TX_AUTO_COPY_EN & 0x7F; -+ buf[1] = 0xFF; -+ CTP_SPI_READ(ts->client, buf, 2); -+ -+ if (buf[1] == 0x00) -+ break; -+ -+ usleep_range(1000, 1000); -+ } -+ -+ if (i >= retry) { -+ NVT_ERR("failed, i=%d, buf[1]=0x%02X\n", i, buf[1]); -+ return -1; -+ } else { -+ return 0; -+ } -+} -+ -+int32_t nvt_wait_auto_copy(void) -+{ -+ if (ts->auto_copy == CHECK_SPI_DMA_TX_INFO) { -+ return nvt_check_spi_dma_tx_info(); -+ } else if (ts->auto_copy == CHECK_TX_AUTO_COPY_EN) { -+ return nvt_check_tx_auto_copy(); -+ } else { -+ NVT_ERR("failed, not support mode %d!\n", ts->auto_copy); -+ return -1; -+ } -+} -+ -+int32_t disable_pen_input_device(bool disable) { -+ uint8_t buf[8] = {0}; -+ int32_t ret = 0; -+ -+ NVT_LOG("++\n"); -+ if (!bTouchIsAwake || !ts) { -+ NVT_LOG("touch suspend, stop set pen state %s", disable ? "DISABLE" : "ENABLE"); -+ goto nvt_set_pen_enable_out; -+ } -+ -+ msleep(35); -+ disable = (!(ts->pen_input_dev_enable) || ts->pen_is_charge) ? true : disable; -+ -+ //---set xdata index to EVENT BUF ADDR--- -+ ret = nvt_set_page(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_HOST_CMD); -+ if (ret < 0) { -+ NVT_ERR("Set event buffer index fail!\n"); -+ goto nvt_set_pen_enable_out; -+ } -+ -+ buf[0] = EVENT_MAP_HOST_CMD; -+ buf[1] = 0x7B; -+ buf[2] = !!disable; -+ ret = CTP_SPI_WRITE(ts->client, buf, 3); -+ if (ret < 0) { -+ NVT_ERR("set pen %s failed!\n", disable ? "DISABLE" : "ENABLE"); -+ goto nvt_set_pen_enable_out; -+ } -+ NVT_LOG("pen charge state is %s, %s pen input device\n", -+ ts->pen_is_charge ? "ENABLE" : "DISABLE", -+ disable ? "DISABLE" : "ENABLE"); -+ -+nvt_set_pen_enable_out: -+ NVT_LOG("--\n"); -+ return ret; -+} -+ - static void nvt_suspend_work(struct work_struct *work) - { - struct nvt_ts_data *ts_core = container_of(work, struct nvt_ts_data, suspend_work); -@@ -1292,8 +1297,6 @@ static int32_t nvt_ts_probe(struct spi_device *client) - } - } - -- ts->abs_x_max = TOUCH_DEFAULT_MAX_WIDTH; -- ts->abs_y_max = TOUCH_DEFAULT_MAX_HEIGHT; - - //---allocate input device--- - ts->input_dev = input_allocate_device(); -@@ -1322,8 +1325,6 @@ static int32_t nvt_ts_probe(struct spi_device *client) - ts->y_num = 50; - ts->x_gang_num = 4; - ts->y_gang_num = 6; -- ts->abs_x_max = TOUCH_DEFAULT_MAX_WIDTH; -- ts->abs_y_max = TOUCH_DEFAULT_MAX_HEIGHT; - ts->max_button_num = TOUCH_KEY_NUM; - NVT_LOG("Set default fw_ver=%d, x_num=%d, y_num=%d, " - "abs_x_max=%d, abs_y_max=%d, max_button_num=%d!\n", -@@ -1384,14 +1385,21 @@ static int32_t nvt_ts_probe(struct spi_device *client) - ts->pen_input_dev->keybit[BIT_WORD(BTN_STYLUS2)] |= BIT_MASK(BTN_STYLUS2); - ts->pen_input_dev->propbit[0] = BIT(INPUT_PROP_DIRECT); - -+ int x_max, y_max; -+ - if (ts->wgp_stylus) { -- input_set_abs_params(ts->pen_input_dev, ABS_X, 0, ts->abs_x_max * 2 - 1, 0, 0); -- input_set_abs_params(ts->pen_input_dev, ABS_Y, 0, ts->abs_y_max * 2 - 1, 0, 0); -+ x_max = ts->abs_x_max * 2 - 1; -+ y_max = ts->abs_y_max * 2 - 1; - } else { -- input_set_abs_params(ts->pen_input_dev, ABS_X, 0, ts->abs_x_max - 1, 0, 0); -- input_set_abs_params(ts->pen_input_dev, ABS_Y, 0, ts->abs_y_max - 1, 0, 0); -+ x_max = ts->abs_x_max - 1; -+ y_max = ts->abs_y_max - 1; - } - -+ input_set_abs_params(ts->pen_input_dev, ABS_X, 0, x_max, 0, 0); -+ input_set_abs_params(ts->pen_input_dev, ABS_Y, 0, y_max , 0, 0); -+ input_abs_set_res(ts->pen_input_dev, ABS_X, x_max / PANEL_DEFAULT_WIDTH_MM); -+ input_abs_set_res(ts->pen_input_dev, ABS_Y, y_max / PANEL_DEFAULT_HEIGHT_MM); -+ - input_set_abs_params(ts->pen_input_dev, ABS_PRESSURE, 0, PEN_PRESSURE_MAX, 0, 0); - input_set_abs_params(ts->pen_input_dev, ABS_DISTANCE, 0, PEN_DISTANCE_MAX, 0, 0); - input_set_abs_params(ts->pen_input_dev, ABS_TILT_X, PEN_TILT_MIN, PEN_TILT_MAX, 0, 0); -@@ -1437,11 +1445,11 @@ static int32_t nvt_ts_probe(struct spi_device *client) - init_completion(&ts->dev_pm_suspend_completion); - ts->fw_debug = false; - --#ifdef CONFIG_FACTORY_BUILD -+//#ifdef CONFIG_FACTORY_BUILD - ts->pen_input_dev_enable = 1; --#else -- ts->pen_input_dev_enable = 0; --#endif -+//#else -+// ts->pen_input_dev_enable = 0; -+//#endif - - #if BOOT_UPDATE_FIRMWARE - nvt_fwu_wq = alloc_workqueue("nvt_fwu_wq", WQ_UNBOUND | WQ_MEM_RECLAIM, 1); -@@ -1701,6 +1709,7 @@ static int32_t nvt_ts_suspend(struct device *dev) - - if (ts->pen_input_dev_enable) { - NVT_LOG("if enable pen,will close it"); -+ disable_pen_input_device(true); - } - - if (ts->db_wakeup) { -@@ -1769,6 +1778,12 @@ static int32_t nvt_ts_resume(struct device *dev) - if (ts->dev_pm_suspend) - pm_stay_awake(dev); - -+ // Xiaomi Pad 6 panel has some delay before turning on -+ if (ts->desc->input_calc_method == NVT_INPUT_CALC_NT36532) -+ { -+ msleep(750); -+ } -+ - mutex_lock(&ts->lock); - - NVT_LOG("resume start\n"); -@@ -1798,6 +1813,7 @@ static int32_t nvt_ts_resume(struct device *dev) - - mutex_unlock(&ts->lock); - -+ disable_pen_input_device(false); - if (likely(ts->ic_state == NVT_IC_RESUME_IN)) { - ts->ic_state = NVT_IC_RESUME_OUT; - } else { -@@ -1874,16 +1890,33 @@ static const struct dev_pm_ops nvt_dev_pm_ops = { - }; - - static const struct spi_device_id nvt_ts_id[] = { -- { NVT_SPI_NAME, 0 }, -+ { "NVT-ts-spi", 0 }, -+ { "NVT-ts-spi-nt36532", 0 }, - { } - }; - MODULE_DEVICE_TABLE(spi, nvt_ts_id); - - #ifdef CONFIG_OF -+ -+static const struct nvt_ts_desc nt36523_desc = { -+ .mmap = &NT36523_memory_map, -+ .hw_crc = HWCRC_LEN_3Bytes, -+ .auto_copy = CHECK_SPI_DMA_TX_INFO, -+ .input_calc_method = NVT_INPUT_CALC_NT36523, -+}; -+static const struct nvt_ts_desc nt36532_desc = { -+ .mmap = &NT36532_cascade_memory_map, -+ .hw_crc = HWCRC_LEN_3Bytes, -+ .auto_copy = CHECK_TX_AUTO_COPY_EN, -+ .input_calc_method = NVT_INPUT_CALC_NT36532, -+}; -+ - static struct of_device_id nvt_match_table[] = { -- { .compatible = "novatek,NVT-ts-spi",}, -+ { .compatible = "novatek,NVT-ts-spi", .data = &nt36523_desc }, -+ { .compatible = "novatek,NVT-ts-spi-nt36532", .data = &nt36532_desc }, - { }, - }; -+ - MODULE_DEVICE_TABLE(of, nvt_match_table); - #endif - -diff --git a/drivers/input/touchscreen/nt36523/nt36xxx.h b/drivers/input/touchscreen/nt36523/nt36xxx.h -index 6642ec2f26cf..c826308a5492 100644 ---- a/drivers/input/touchscreen/nt36523/nt36xxx.h -+++ b/drivers/input/touchscreen/nt36523/nt36xxx.h -@@ -70,7 +70,9 @@ extern const uint16_t touch_key_array[TOUCH_KEY_NUM]; - #define PEN_DISTANCE_MAX (1) - #define PEN_TILT_MIN (-60) - #define PEN_TILT_MAX (60) -- -+//---for pen resolution--- -+#define PANEL_DEFAULT_WIDTH_MM 148 // 148mm -+#define PANEL_DEFAULT_HEIGHT_MM 237 // 237mm - /* Enable only when module have tp reset pin and connected to host */ - #define NVT_TOUCH_SUPPORT_HW_RST 0 - -@@ -109,6 +111,18 @@ struct nvt_config_info { - const char *nvt_limit_name; - }; - -+enum nvt_input_calc_method { -+ NVT_INPUT_CALC_NT36523, -+ NVT_INPUT_CALC_NT36532, -+}; -+ -+struct nvt_ts_desc { -+ const struct nvt_ts_mem_map *mmap; -+ uint8_t hw_crc; -+ uint8_t auto_copy; -+ enum nvt_input_calc_method input_calc_method; -+}; -+ - struct nvt_ts_data { - struct spi_device *client; - struct input_dev *input_dev; -@@ -128,16 +142,18 @@ struct nvt_ts_data { - #endif - uint32_t config_array_size; - struct nvt_config_info *config_array; -+ const struct nvt_ts_desc *desc; - const char *fw_name; - bool lkdown_readed; - uint8_t fw_ver; - uint8_t x_num; - uint8_t y_num; - int ic_state; -- uint16_t abs_x_max; -- uint16_t abs_y_max; -+ uint32_t abs_x_max; -+ uint32_t abs_y_max; - uint8_t max_touch_num; - uint8_t max_button_num; -+ uint8_t auto_copy; - uint32_t int_trigger_type; - int32_t irq_gpio; - uint32_t irq_flags; -@@ -229,12 +245,15 @@ int32_t nvt_get_fw_info(void); - int32_t nvt_clear_fw_status(void); - int32_t nvt_check_fw_status(void); - int32_t nvt_check_spi_dma_tx_info(void); -+int32_t nvt_check_tx_auto_copy(void); - int32_t nvt_set_page(uint32_t addr); - int32_t nvt_write_addr(uint32_t addr, uint8_t data); - int32_t nvt_read_pid(void); - bool nvt_get_dbgfw_status(void); - int32_t nvt_set_pocket_palm_switch(uint8_t pocket_palm_switch); - void Boot_Update_Firmware(struct work_struct *work); -+int32_t nvt_wait_auto_copy(void); -+int32_t disable_pen_input_device(bool disable); - #if NVT_TOUCH_ESD_PROTECT - extern void nvt_esd_check_enable(uint8_t enable); - #endif /* #if NVT_TOUCH_ESD_PROTECT */ -diff --git a/drivers/input/touchscreen/nt36523/nt36xxx_fw_update.c b/drivers/input/touchscreen/nt36523/nt36xxx_fw_update.c -index 4f383dac2c3c..25e6b6f2da60 100644 ---- a/drivers/input/touchscreen/nt36523/nt36xxx_fw_update.c -+++ b/drivers/input/touchscreen/nt36523/nt36xxx_fw_update.c -@@ -1,9 +1,8 @@ - /* -- * Copyright (C) 2010 - 2018 Novatek, Inc. -- * Copyright (C) 2021 XiaoMi, Inc. -+ * Copyright (C) 2010 - 2022 Novatek, Inc. - * -- * $Revision: 68983 $ -- * $Date: 2020-09-17 09:43:23 +0800 (週四, 17 九月 2020) $ -+ * $Revision: 77624 $ -+ * $Date: 2021-02-05 10:03:05 +0800 (週五, 05 二月 2021) $ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by -@@ -23,14 +22,12 @@ - #include "nt36xxx.h" - - #if BOOT_UPDATE_FIRMWARE -- - #define SIZE_4KB 4096 -+#define NVT_FLASH_END_FLAG_LEN 3 - #define FLASH_SECTOR_SIZE SIZE_4KB - #define FW_BIN_VER_OFFSET (fw_need_write_size - SIZE_4KB) - #define FW_BIN_VER_BAR_OFFSET (FW_BIN_VER_OFFSET + 1) --#define NVT_FLASH_END_FLAG_LEN 3 --#define NVT_FLASH_END_FLAG_ADDR (fw_need_write_size - NVT_FLASH_END_FLAG_LEN) -- -+#define DEFAULT_DEBUG_FW_NAME "novatek_debug_fw.bin" - static ktime_t start, end; - const struct firmware *fw_entry = NULL; - static size_t fw_need_write_size = 0; -@@ -46,6 +43,35 @@ struct nvt_ts_bin_map { - - static struct nvt_ts_bin_map *bin_map; - -+static int32_t nvt_get_fw_need_write_size(const struct firmware *fw_entry) -+{ -+ int32_t i = 0; -+ int32_t total_sectors_to_check = 0; -+ -+ total_sectors_to_check = fw_entry->size / FLASH_SECTOR_SIZE; -+ /* printk("total_sectors_to_check = %d\n", total_sectors_to_check); */ -+ -+ for (i = total_sectors_to_check; i > 0; i--) { -+ /* printk("current end flag address checked = 0x%X\n", i * FLASH_SECTOR_SIZE - NVT_FLASH_END_FLAG_LEN); */ -+ /* check if there is end flag "NVT" at the end of this sector */ -+ if (strncmp(&fw_entry->data[i * FLASH_SECTOR_SIZE - NVT_FLASH_END_FLAG_LEN], "NVT", NVT_FLASH_END_FLAG_LEN) == 0) { -+ fw_need_write_size = i * FLASH_SECTOR_SIZE; -+ NVT_LOG("fw_need_write_size = %zu(0x%zx), NVT end flag\n", fw_need_write_size, fw_need_write_size); -+ return 0; -+ } -+ -+ /* check if there is end flag "MOD" at the end of this sector */ -+ if (strncmp(&fw_entry->data[i * FLASH_SECTOR_SIZE - NVT_FLASH_END_FLAG_LEN], "MOD", NVT_FLASH_END_FLAG_LEN) == 0) { -+ fw_need_write_size = i * FLASH_SECTOR_SIZE; -+ NVT_LOG("fw_need_write_size = %zu(0x%zx), MOD end flag\n", fw_need_write_size, fw_need_write_size); -+ return 0; -+ } -+ } -+ -+ NVT_ERR("end flag \"NVT\" \"MOD\" not found!\n"); -+ return -1; -+} -+ - /******************************************************* - Description: - Novatek touchscreen init variable and allocate buffer -@@ -307,7 +333,12 @@ static int32_t update_firmware_request(const char *filename) - goto request_fail; - } - -- fw_need_write_size = fw_entry->size; -+ // check FW need to write size -+ if (nvt_get_fw_need_write_size(fw_entry)) { -+ NVT_ERR("get fw need to write size fail!\n"); -+ ret = -EINVAL; -+ goto invalid; -+ } - - // check if FW version add FW version bar equals 0xFF - if (*(fw_entry->data + FW_BIN_VER_OFFSET) + *(fw_entry->data + FW_BIN_VER_BAR_OFFSET) != 0xFF) { -@@ -524,10 +555,10 @@ static void nvt_set_bld_crc_bank(uint32_t DES_ADDR, uint32_t SRAM_ADDR, - fwbuf[0] = LENGTH_ADDR & 0x7F; - fwbuf[1] = (size) & 0xFF; - fwbuf[2] = (size >> 8) & 0xFF; -- fwbuf[3] = (size >> 16) & 0x01; -- if (ts->hw_crc == 1) { -+ fwbuf[3] = (size >> 16) & 0xFF; -+ if (ts->hw_crc == HWCRC_LEN_2Bytes) { - CTP_SPI_WRITE(ts->client, fwbuf, 3); -- } else if (ts->hw_crc > 1) { -+ } else if (ts->hw_crc >= HWCRC_LEN_3Bytes) { - CTP_SPI_WRITE(ts->client, fwbuf, 4); - } - -@@ -667,9 +698,9 @@ static int32_t nvt_download_firmware_hw_crc(void) - goto fail; - } - -- ret = nvt_check_spi_dma_tx_info(); -+ ret = nvt_wait_auto_copy(); - if (ret) { -- NVT_ERR("spi dma tx info failed. (%d)\n", ret); -+ NVT_ERR("wait auto copy failed. (%d)\n", ret); - goto fail; - } - } else { -@@ -680,9 +711,6 @@ static int32_t nvt_download_firmware_hw_crc(void) - } - } - -- /* enable hw bld crc function */ -- nvt_bld_crc_enable(); -- - /* clear fw reset status & enable fw crc check */ - nvt_fw_crc_enable(); - -@@ -726,6 +754,9 @@ static int32_t nvt_download_firmware(void) - - start = ktime_get(); - -+ NVT_LOG("Start firmware download\n"); -+ nvt_check_fw_reset_state(0x0A); -+ - while (1) { - /* - * Send eng reset cmd before download FW -@@ -742,6 +773,9 @@ static int32_t nvt_download_firmware(void) - #endif - nvt_bootloader_reset(); - -+ NVT_LOG("Reset bootloader\n"); -+ nvt_check_fw_reset_state(0x0A); -+ - /* clear fw reset status */ - nvt_write_addr(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_RESET_COMPLETE, 0x00); - -@@ -752,6 +786,9 @@ static int32_t nvt_download_firmware(void) - goto fail; - } - -+ NVT_LOG("Written firmware\n"); -+ nvt_check_fw_reset_state(0x0A); -+ - /* Set Boot Ready Bit */ - nvt_boot_ready(); - -@@ -850,7 +887,15 @@ int32_t nvt_update_firmware(const char *firmware_name) - void Boot_Update_Firmware(struct work_struct *work) - { - mutex_lock(&ts->lock); -- nvt_update_firmware(ts->fw_name); -+ if (nvt_get_dbgfw_status()) { -+ if (nvt_update_firmware(DEFAULT_DEBUG_FW_NAME) < 0) { -+ NVT_ERR("use built-in fw"); -+ nvt_update_firmware(ts->fw_name); -+ } -+ } else { -+ nvt_update_firmware(ts->fw_name); -+ } -+ disable_pen_input_device(false); - nvt_get_fw_info(); - mutex_unlock(&ts->lock); - } -diff --git a/drivers/input/touchscreen/nt36523/nt36xxx_mem_map.h b/drivers/input/touchscreen/nt36523/nt36xxx_mem_map.h -index 3f4195d636a0..b4b6fce51a60 100644 ---- a/drivers/input/touchscreen/nt36523/nt36xxx_mem_map.h -+++ b/drivers/input/touchscreen/nt36523/nt36xxx_mem_map.h -@@ -20,6 +20,11 @@ - #define CHIP_VER_TRIM_ADDR 0x3F004 - #define CHIP_VER_TRIM_OLD_ADDR 0x1F64E - -+typedef struct nvt_ts_reg { -+ uint32_t addr; /* byte in which address */ -+ uint8_t mask; /* in which bits of that byte */ -+} nvt_ts_reg_t; -+ - struct nvt_ts_mem_map { - uint32_t EVENT_BUF_ADDR; - uint32_t RAW_PIPE0_ADDR; -@@ -48,8 +53,14 @@ struct nvt_ts_mem_map { - uint32_t PEN_1D_DIFF_TIP_Y_ADDR; - uint32_t PEN_1D_DIFF_RING_X_ADDR; - uint32_t PEN_1D_DIFF_RING_Y_ADDR; -+ nvt_ts_reg_t ENB_CASC_REG; -+ /* FW History */ -+ uint32_t MMAP_HISTORY_EVENT0; -+ uint32_t MMAP_HISTORY_EVENT1; -+ /* START for flash FW update */ - uint32_t READ_FLASH_CHECKSUM_ADDR; - uint32_t RW_FLASH_DATA_ADDR; -+ /* END for FW Update Use */ - /* Phase 2 Host Download */ - uint32_t BOOT_RDY_ADDR; - uint32_t POR_CD_ADDR; -@@ -66,16 +77,242 @@ struct nvt_ts_mem_map { - uint32_t G_DLM_CHECKSUM_ADDR; - uint32_t R_ILM_CHECKSUM_ADDR; - uint32_t R_DLM_CHECKSUM_ADDR; -- uint32_t BLD_CRC_EN_ADDR; - uint32_t DMA_CRC_EN_ADDR; - uint32_t BLD_ILM_DLM_CRC_ADDR; - uint32_t DMA_CRC_FLAG_ADDR; -- uint32_t FW_HISTORY_ADDR; - }; - - struct nvt_ts_hw_info { -- uint8_t carrier_system; - uint8_t hw_crc; -+ uint8_t auto_copy; -+ bool use_gcm; -+ const struct nvt_ts_hw_reg_addr_info *hw_regs; -+}; -+ -+typedef enum { -+ HWCRC_NOSUPPORT = 0x00, -+ HWCRC_LEN_2Bytes = 0x01, -+ HWCRC_LEN_3Bytes = 0x02, -+} HWCRCBankConfig; -+ -+typedef enum { -+ AUTOCOPY_NOSUPPORT = 0x00, -+ CHECK_SPI_DMA_TX_INFO = 0x01, -+ CHECK_TX_AUTO_COPY_EN = 0x02, -+} AUTOCOPYCheck; -+ -+/* hw info reg*/ -+struct nvt_ts_hw_reg_addr_info { -+ uint32_t chip_ver_trim_addr; -+ uint32_t swrst_sif_addr; -+ uint32_t crc_err_flag_addr; -+}; -+ -+static const struct nvt_ts_hw_reg_addr_info hw_reg_addr_info = { -+ .chip_ver_trim_addr = 0x1FB104, -+ .swrst_sif_addr = 0x1FB43E, -+ .crc_err_flag_addr = 0x1FB535, -+}; -+ -+static const struct nvt_ts_hw_reg_addr_info hw_reg_addr_info_old_w_isp = { -+ .chip_ver_trim_addr = 0x3F004, -+ .swrst_sif_addr = 0x3F0FE, -+ .crc_err_flag_addr = 0x3F135, -+}; -+ -+static const struct nvt_ts_hw_reg_addr_info hw_reg_addr_info_legacy_w_isp = { -+ .chip_ver_trim_addr = 0x1F64E, -+ .swrst_sif_addr = 0x1F01A, -+ .crc_err_flag_addr = 0, -+}; -+ -+/* tddi */ -+static const struct nvt_ts_mem_map NT36532_cascade_memory_map = { -+ .EVENT_BUF_ADDR = 0x125800, -+ .RAW_PIPE0_ADDR = 0x10B200, -+ .RAW_PIPE1_ADDR = 0x10B200, -+ .BASELINE_ADDR = 0x109E00, -+ .BASELINE_BTN_ADDR = 0, -+ .DIFF_PIPE0_ADDR = 0x128140, -+ .DIFF_PIPE1_ADDR = 0x129540, -+ .RAW_BTN_PIPE0_ADDR = 0, -+ .RAW_BTN_PIPE1_ADDR = 0, -+ .DIFF_BTN_PIPE0_ADDR = 0, -+ .DIFF_BTN_PIPE1_ADDR = 0, -+ .PEN_2D_BL_TIP_X_ADDR = 0x10F940, -+ .PEN_2D_BL_TIP_Y_ADDR = 0x10FD40, -+ .PEN_2D_BL_RING_X_ADDR = 0x110140, -+ .PEN_2D_BL_RING_Y_ADDR = 0x110540, -+ .PEN_2D_DIFF_TIP_X_ADDR = 0x111140, -+ .PEN_2D_DIFF_TIP_Y_ADDR = 0x111540, -+ .PEN_2D_DIFF_RING_X_ADDR = 0x111940, -+ .PEN_2D_DIFF_RING_Y_ADDR = 0x111D40, -+ .PEN_2D_RAW_TIP_X_ADDR = 0x126E00, -+ .PEN_2D_RAW_TIP_Y_ADDR = 0x127210, -+ .PEN_2D_RAW_RING_X_ADDR = 0x127620, -+ .PEN_2D_RAW_RING_Y_ADDR = 0x127A30, -+ .PEN_1D_DIFF_TIP_X_ADDR = 0x127E40, -+ .PEN_1D_DIFF_TIP_Y_ADDR = 0x127EC0, -+ .PEN_1D_DIFF_RING_X_ADDR = 0x127F40, -+ .PEN_1D_DIFF_RING_Y_ADDR = 0x127FC0, -+ .ENB_CASC_REG = {.addr = 0x1FB12C, .mask = 0x01}, -+ /* FW History */ -+ .MMAP_HISTORY_EVENT0 = 0x121AFC, -+ .MMAP_HISTORY_EVENT1 = 0x121B3C, -+ /* Phase 2 Host Download */ -+ .BOOT_RDY_ADDR = 0x1FB50D, -+ .TX_AUTO_COPY_EN = 0x1FC925, -+ .SPI_DMA_TX_INFO = 0x1FC914, -+ /* BLD CRC */ -+ .BLD_LENGTH_ADDR = 0x1FB538, //0x1FB538 ~ 0x1FB53A (3 bytes) -+ .ILM_LENGTH_ADDR = 0x1FB518, //0x1FB518 ~ 0x1FB51A (3 bytes) -+ .DLM_LENGTH_ADDR = 0x1FB530, //0x1FB530 ~ 0x1FB532 (3 bytes) -+ .BLD_DES_ADDR = 0x1FB514, //0x1FB514 ~ 0x1FB516 (3 bytes) -+ .ILM_DES_ADDR = 0x1FB528, //0x1FB528 ~ 0x1FB52A (3 bytes) -+ .DLM_DES_ADDR = 0x1FB52C, //0x1FB52C ~ 0x1FB52E (3 bytes) -+ .G_ILM_CHECKSUM_ADDR = 0x1FB500, //0x1FB500 ~ 0x1FB503 (4 bytes) -+ .G_DLM_CHECKSUM_ADDR = 0x1FB504, //0x1FB504 ~ 0x1FB507 (4 bytes) -+ .R_ILM_CHECKSUM_ADDR = 0x1FB520, //0x1FB520 ~ 0x1FB523 (4 bytes) -+ .R_DLM_CHECKSUM_ADDR = 0x1FB524, //0x1FB524 ~ 0x1FB527 (4 bytes) -+ .DMA_CRC_EN_ADDR = 0x1FB536, -+ .BLD_ILM_DLM_CRC_ADDR = 0x1FB533, -+ .DMA_CRC_FLAG_ADDR = 0x1FB534, -+}; -+ -+static const struct nvt_ts_mem_map NT36532_single_memory_map = { -+ .EVENT_BUF_ADDR = 0x125800, -+ .RAW_PIPE0_ADDR = 0x10C1EC, -+ .RAW_PIPE1_ADDR = 0x10C1EC, -+ .BASELINE_ADDR = 0x10B1EC, -+ .BASELINE_BTN_ADDR = 0, -+ .DIFF_PIPE0_ADDR = 0x11BFC4, -+ .DIFF_PIPE1_ADDR = 0x11CFC4, -+ .RAW_BTN_PIPE0_ADDR = 0, -+ .RAW_BTN_PIPE1_ADDR = 0, -+ .DIFF_BTN_PIPE0_ADDR = 0, -+ .DIFF_BTN_PIPE1_ADDR = 0, -+ .PEN_2D_BL_TIP_X_ADDR = 0x11E5EC, -+ .PEN_2D_BL_TIP_Y_ADDR = 0x126C00, -+ .PEN_2D_BL_RING_X_ADDR = 0x11E7EC, -+ .PEN_2D_BL_RING_Y_ADDR = 0x126E00, -+ .PEN_2D_DIFF_TIP_X_ADDR = 0x11E1EC, -+ .PEN_2D_DIFF_TIP_Y_ADDR = 0x11E9EC, -+ .PEN_2D_DIFF_RING_X_ADDR = 0x11E3EC, -+ .PEN_2D_DIFF_RING_Y_ADDR = 0x11EBEC, -+ .PEN_2D_RAW_TIP_X_ADDR = 0x120CEC, -+ .PEN_2D_RAW_TIP_Y_ADDR = 0x120EFC, -+ .PEN_2D_RAW_RING_X_ADDR = 0x12110C, -+ .PEN_2D_RAW_RING_Y_ADDR = 0x12131C, -+ .PEN_1D_DIFF_TIP_X_ADDR = 0x126A00, -+ .PEN_1D_DIFF_TIP_Y_ADDR = 0x126A80, -+ .PEN_1D_DIFF_RING_X_ADDR = 0x126B00, -+ .PEN_1D_DIFF_RING_Y_ADDR = 0x126B80, -+ .ENB_CASC_REG = {.addr = 0x1FB12C, .mask = 0x01}, -+ /* FW History */ -+ .MMAP_HISTORY_EVENT0 = 0x122930, -+ .MMAP_HISTORY_EVENT1 = 0x122970, -+ /* Phase 2 Host Download */ -+ .BOOT_RDY_ADDR = 0x1FB50D, -+ .TX_AUTO_COPY_EN = 0x1FC925, -+ .SPI_DMA_TX_INFO = 0x1FC914, -+ /* BLD CRC */ -+ .BLD_LENGTH_ADDR = 0x1FB538, //0x1FB538 ~ 0x1FB53A (3 bytes) -+ .ILM_LENGTH_ADDR = 0x1FB518, //0x1FB518 ~ 0x1FB51A (3 bytes) -+ .DLM_LENGTH_ADDR = 0x1FB530, //0x1FB530 ~ 0x1FB532 (3 bytes) -+ .BLD_DES_ADDR = 0x1FB514, //0x1FB514 ~ 0x1FB516 (3 bytes) -+ .ILM_DES_ADDR = 0x1FB528, //0x1FB528 ~ 0x1FB52A (3 bytes) -+ .DLM_DES_ADDR = 0x1FB52C, //0x1FB52C ~ 0x1FB52E (3 bytes) -+ .G_ILM_CHECKSUM_ADDR = 0x1FB500, //0x1FB500 ~ 0x1FB503 (4 bytes) -+ .G_DLM_CHECKSUM_ADDR = 0x1FB504, //0x1FB504 ~ 0x1FB507 (4 bytes) -+ .R_ILM_CHECKSUM_ADDR = 0x1FB520, //0x1FB520 ~ 0x1FB523 (4 bytes) -+ .R_DLM_CHECKSUM_ADDR = 0x1FB524, //0x1FB524 ~ 0x1FB527 (4 bytes) -+ .DMA_CRC_EN_ADDR = 0x1FB536, -+ .BLD_ILM_DLM_CRC_ADDR = 0x1FB533, -+ .DMA_CRC_FLAG_ADDR = 0x1FB534, -+}; -+ -+static const struct nvt_ts_mem_map NT36523N_memory_map = { -+ .EVENT_BUF_ADDR = 0x2FD00, -+ .RAW_PIPE0_ADDR = 0x30FA0, -+ .RAW_PIPE1_ADDR = 0x30FA0, -+ .BASELINE_ADDR = 0x36510, -+ .BASELINE_BTN_ADDR = 0, -+ .DIFF_PIPE0_ADDR = 0x373E8, -+ .DIFF_PIPE1_ADDR = 0x38068, -+ .RAW_BTN_PIPE0_ADDR = 0, -+ .RAW_BTN_PIPE1_ADDR = 0, -+ .DIFF_BTN_PIPE0_ADDR = 0, -+ .DIFF_BTN_PIPE1_ADDR = 0, -+ .PEN_2D_BL_TIP_X_ADDR = 0x2988A, -+ .PEN_2D_BL_TIP_Y_ADDR = 0x29A1A, -+ .PEN_2D_BL_RING_X_ADDR = 0x29BAA, -+ .PEN_2D_BL_RING_Y_ADDR = 0x29D3A, -+ .PEN_2D_DIFF_TIP_X_ADDR = 0x29ECA, -+ .PEN_2D_DIFF_TIP_Y_ADDR = 0x2A05A, -+ .PEN_2D_DIFF_RING_X_ADDR = 0x2A1EA, -+ .PEN_2D_DIFF_RING_Y_ADDR = 0x2A37A, -+ .PEN_2D_RAW_TIP_X_ADDR = 0x2A50A, -+ .PEN_2D_RAW_TIP_Y_ADDR = 0x2A69A, -+ .PEN_2D_RAW_RING_X_ADDR = 0x2A82A, -+ .PEN_2D_RAW_RING_Y_ADDR = 0x2A9BA, -+ .PEN_1D_DIFF_TIP_X_ADDR = 0x2AB4A, -+ .PEN_1D_DIFF_TIP_Y_ADDR = 0x2ABAE, -+ .PEN_1D_DIFF_RING_X_ADDR = 0x2AC12, -+ .PEN_1D_DIFF_RING_Y_ADDR = 0x2AC76, -+ /* FW History */ -+ .MMAP_HISTORY_EVENT0 = 0x38D54, -+ .MMAP_HISTORY_EVENT1 = 0x38D94, -+ /* Phase 2 Host Download */ -+ .BOOT_RDY_ADDR = 0x3F10D, -+ .TX_AUTO_COPY_EN = 0x3F7E8, -+ .SPI_DMA_TX_INFO = 0x3F7F1, -+ /* BLD CRC */ -+ .BLD_LENGTH_ADDR = 0x3F138, //0x3F138 ~ 0x3F13A (3 bytes) -+ .ILM_LENGTH_ADDR = 0x3F118, //0x3F118 ~ 0x3F11A (3 bytes) -+ .DLM_LENGTH_ADDR = 0x3F130, //0x3F130 ~ 0x3F132 (3 bytes) -+ .BLD_DES_ADDR = 0x3F114, //0x3F114 ~ 0x3F116 (3 bytes) -+ .ILM_DES_ADDR = 0x3F128, //0x3F128 ~ 0x3F12A (3 bytes) -+ .DLM_DES_ADDR = 0x3F12C, //0x3F12C ~ 0x3F12E (3 bytes) -+ .G_ILM_CHECKSUM_ADDR = 0x3F100, //0x3F100 ~ 0x3F103 (4 bytes) -+ .G_DLM_CHECKSUM_ADDR = 0x3F104, //0x3F104 ~ 0x3F107 (4 bytes) -+ .R_ILM_CHECKSUM_ADDR = 0x3F120, //0x3F120 ~ 0x3F123 (4 bytes) -+ .R_DLM_CHECKSUM_ADDR = 0x3F124, //0x3F124 ~ 0x3F127 (4 bytes) -+ .DMA_CRC_EN_ADDR = 0x3F136, -+ .BLD_ILM_DLM_CRC_ADDR = 0x3F133, -+ .DMA_CRC_FLAG_ADDR = 0x3F134, -+}; -+ -+static const struct nvt_ts_mem_map NT36528_memory_map = { -+ .EVENT_BUF_ADDR = 0x22D00, -+ .RAW_PIPE0_ADDR = 0x24000, -+ .RAW_PIPE1_ADDR = 0x24000, -+ .BASELINE_ADDR = 0x21880, -+ .BASELINE_BTN_ADDR = 0, -+ .DIFF_PIPE0_ADDR = 0x20B00, -+ .DIFF_PIPE1_ADDR = 0x24B00, -+ .RAW_BTN_PIPE0_ADDR = 0, -+ .RAW_BTN_PIPE1_ADDR = 0, -+ .DIFF_BTN_PIPE0_ADDR = 0, -+ .DIFF_BTN_PIPE1_ADDR = 0, -+ /* FW History */ -+ .MMAP_HISTORY_EVENT0 = 0x23768, -+ .MMAP_HISTORY_EVENT1 = 0x237A8, -+ /* Phase 2 Host Download */ -+ .BOOT_RDY_ADDR = 0x3F10D, -+ /* BLD CRC */ -+ .BLD_LENGTH_ADDR = 0x3F138, //0x3F138 ~ 0x3F13A (3 bytes) -+ .ILM_LENGTH_ADDR = 0x3F118, //0x3F118 ~ 0x3F11A (3 bytes) -+ .DLM_LENGTH_ADDR = 0x3F130, //0x3F130 ~ 0x3F132 (3 bytes) -+ .BLD_DES_ADDR = 0x3F114, //0x3F114 ~ 0x3F116 (3 bytes) -+ .ILM_DES_ADDR = 0x3F128, //0x3F128 ~ 0x3F12A (3 bytes) -+ .DLM_DES_ADDR = 0x3F12C, //0x3F12C ~ 0x3F12E (3 bytes) -+ .G_ILM_CHECKSUM_ADDR = 0x3F100, //0x3F100 ~ 0x3F103 (4 bytes) -+ .G_DLM_CHECKSUM_ADDR = 0x3F104, //0x3F104 ~ 0x3F107 (4 bytes) -+ .R_ILM_CHECKSUM_ADDR = 0x3F120, //0x3F120 ~ 0x3F123 (4 bytes) -+ .R_DLM_CHECKSUM_ADDR = 0x3F124, //0x3F124 ~ 0x3F127 (4 bytes) -+ .DMA_CRC_EN_ADDR = 0x3F136, -+ .BLD_ILM_DLM_CRC_ADDR = 0x3F133, -+ .DMA_CRC_FLAG_ADDR = 0x3F134, - }; - - static const struct nvt_ts_mem_map NT36523_memory_map = { -@@ -106,8 +343,9 @@ static const struct nvt_ts_mem_map NT36523_memory_map = { - .PEN_1D_DIFF_TIP_Y_ADDR = 0x2ABAE, - .PEN_1D_DIFF_RING_X_ADDR = 0x2AC12, - .PEN_1D_DIFF_RING_Y_ADDR = 0x2AC76, -- .READ_FLASH_CHECKSUM_ADDR = 0x24000, -- .RW_FLASH_DATA_ADDR = 0x24002, -+ /* FW History */ -+ .MMAP_HISTORY_EVENT0 = 0x38D54, -+ .MMAP_HISTORY_EVENT1 = 0x38D94, - /* Phase 2 Host Download */ - .BOOT_RDY_ADDR = 0x3F10D, - .TX_AUTO_COPY_EN = 0x3F7E8, -@@ -123,11 +361,9 @@ static const struct nvt_ts_mem_map NT36523_memory_map = { - .G_DLM_CHECKSUM_ADDR = 0x3F104, //0x3F104 ~ 0x3F107 (4 bytes) - .R_ILM_CHECKSUM_ADDR = 0x3F120, //0x3F120 ~ 0x3F123 (4 bytes) - .R_DLM_CHECKSUM_ADDR = 0x3F124, //0x3F124 ~ 0x3F127 (4 bytes) -- .BLD_CRC_EN_ADDR = 0x3F30E, - .DMA_CRC_EN_ADDR = 0x3F136, - .BLD_ILM_DLM_CRC_ADDR = 0x3F133, - .DMA_CRC_FLAG_ADDR = 0x3F134, -- .FW_HISTORY_ADDR = 0x38D54, - }; - - static const struct nvt_ts_mem_map NT36526_memory_map = { -@@ -142,8 +378,9 @@ static const struct nvt_ts_mem_map NT36526_memory_map = { - .RAW_BTN_PIPE1_ADDR = 0, - .DIFF_BTN_PIPE0_ADDR = 0, - .DIFF_BTN_PIPE1_ADDR = 0, -- .READ_FLASH_CHECKSUM_ADDR = 0x24000, -- .RW_FLASH_DATA_ADDR = 0x24002, -+ /* FW History */ -+ .MMAP_HISTORY_EVENT0 = 0x23C38, -+ .MMAP_HISTORY_EVENT1 = 0x23C78, - /* Phase 2 Host Download */ - .BOOT_RDY_ADDR = 0x3F10D, - /* BLD CRC */ -@@ -157,7 +394,6 @@ static const struct nvt_ts_mem_map NT36526_memory_map = { - .G_DLM_CHECKSUM_ADDR = 0x3F104, //0x3F104 ~ 0x3F107 (4 bytes) - .R_ILM_CHECKSUM_ADDR = 0x3F120, //0x3F120 ~ 0x3F123 (4 bytes) - .R_DLM_CHECKSUM_ADDR = 0x3F124, //0x3F124 ~ 0x3F127 (4 bytes) -- .BLD_CRC_EN_ADDR = 0x3F30E, - .DMA_CRC_EN_ADDR = 0x3F136, - .BLD_ILM_DLM_CRC_ADDR = 0x3F133, - .DMA_CRC_FLAG_ADDR = 0x3F134, -@@ -176,8 +412,9 @@ static const struct nvt_ts_mem_map NT36675_memory_map = { - .RAW_BTN_PIPE1_ADDR = 0, - .DIFF_BTN_PIPE0_ADDR = 0, - .DIFF_BTN_PIPE1_ADDR = 0, -- .READ_FLASH_CHECKSUM_ADDR = 0x24000, -- .RW_FLASH_DATA_ADDR = 0x24002, -+ /* FW History */ -+ .MMAP_HISTORY_EVENT0 = 0x23D10, -+ .MMAP_HISTORY_EVENT1 = 0x23D50, - /* Phase 2 Host Download */ - .BOOT_RDY_ADDR = 0x3F10D, - /* BLD CRC */ -@@ -191,13 +428,11 @@ static const struct nvt_ts_mem_map NT36675_memory_map = { - .G_DLM_CHECKSUM_ADDR = 0x3F104, //0x3F104 ~ 0x3F107 (4 bytes) - .R_ILM_CHECKSUM_ADDR = 0x3F120, //0x3F120 ~ 0x3F123 (4 bytes) - .R_DLM_CHECKSUM_ADDR = 0x3F124, //0x3F124 ~ 0x3F127 (4 bytes) -- .BLD_CRC_EN_ADDR = 0x3F30E, - .DMA_CRC_EN_ADDR = 0x3F136, - .BLD_ILM_DLM_CRC_ADDR = 0x3F133, - .DMA_CRC_FLAG_ADDR = 0x3F134, - }; - -- - static const struct nvt_ts_mem_map NT36672A_memory_map = { - .EVENT_BUF_ADDR = 0x21C00, - .RAW_PIPE0_ADDR = 0x20000, -@@ -210,8 +445,9 @@ static const struct nvt_ts_mem_map NT36672A_memory_map = { - .RAW_BTN_PIPE1_ADDR = 0x23510, - .DIFF_BTN_PIPE0_ADDR = 0x20BF0, - .DIFF_BTN_PIPE1_ADDR = 0x23BF0, -- .READ_FLASH_CHECKSUM_ADDR = 0x24000, -- .RW_FLASH_DATA_ADDR = 0x24002, -+ /* FW History */ -+ .MMAP_HISTORY_EVENT0 = 0x218D6, -+ .MMAP_HISTORY_EVENT1 = 0x24B2D, - /* Phase 2 Host Download */ - .BOOT_RDY_ADDR = 0x3F10D, - /* BLD CRC */ -@@ -225,7 +461,6 @@ static const struct nvt_ts_mem_map NT36672A_memory_map = { - .G_DLM_CHECKSUM_ADDR = 0x3F104, //0x3F104 ~ 0x3F107 (4 bytes) - .R_ILM_CHECKSUM_ADDR = 0x3F120, //0x3F120 ~ 0x3F123 (4 bytes) - .R_DLM_CHECKSUM_ADDR = 0x3F124, //0x3F124 ~ 0x3F127 (4 bytes) -- .BLD_CRC_EN_ADDR = 0x3F30E, - .DMA_CRC_EN_ADDR = 0x3F132, - .BLD_ILM_DLM_CRC_ADDR = 0x3F133, - .DMA_CRC_FLAG_ADDR = 0x3F134, -@@ -243,8 +478,9 @@ static const struct nvt_ts_mem_map NT36772_memory_map = { - .RAW_BTN_PIPE1_ADDR = 0x12E60, - .DIFF_BTN_PIPE0_ADDR = 0x10E68, - .DIFF_BTN_PIPE1_ADDR = 0x12E68, -- .READ_FLASH_CHECKSUM_ADDR = 0x14000, -- .RW_FLASH_DATA_ADDR = 0x14002, -+ /* FW History */ -+ .MMAP_HISTORY_EVENT0 = 0, -+ .MMAP_HISTORY_EVENT1 = 0, - /* Phase 2 Host Download */ - .BOOT_RDY_ADDR = 0x1F141, - .POR_CD_ADDR = 0x1F61C, -@@ -264,8 +500,9 @@ static const struct nvt_ts_mem_map NT36525_memory_map = { - .RAW_BTN_PIPE1_ADDR = 0x12634, - .DIFF_BTN_PIPE0_ADDR = 0x10AFC, - .DIFF_BTN_PIPE1_ADDR = 0x12AFC, -- .READ_FLASH_CHECKSUM_ADDR = 0x14000, -- .RW_FLASH_DATA_ADDR = 0x14002, -+ /* FW History */ -+ .MMAP_HISTORY_EVENT0 = 0, -+ .MMAP_HISTORY_EVENT1 = 0, - /* Phase 2 Host Download */ - .BOOT_RDY_ADDR = 0x1F141, - .POR_CD_ADDR = 0x1F61C, -@@ -285,43 +522,69 @@ static const struct nvt_ts_mem_map NT36676F_memory_map = { - .RAW_BTN_PIPE1_ADDR = 0x12634, - .DIFF_BTN_PIPE0_ADDR = 0x10AFC, - .DIFF_BTN_PIPE1_ADDR = 0x12AFC, -- .READ_FLASH_CHECKSUM_ADDR = 0x14000, -- .RW_FLASH_DATA_ADDR = 0x14002, -+ /* FW History */ -+ .MMAP_HISTORY_EVENT0 = 0, -+ .MMAP_HISTORY_EVENT1 = 0, -+ /* Phase 2 Host Download */ -+ .BOOT_RDY_ADDR = 0x1F141, -+ .POR_CD_ADDR = 0x1F61C, -+ /* BLD CRC */ -+ .R_ILM_CHECKSUM_ADDR = 0x1BF00, -+}; -+ -+static struct nvt_ts_hw_info NT36532_hw_info = { -+ .hw_crc = HWCRC_LEN_3Bytes, -+ .auto_copy = CHECK_TX_AUTO_COPY_EN, -+ .use_gcm = 1, -+ .hw_regs = &hw_reg_addr_info, -+}; -+ -+static struct nvt_ts_hw_info NT36528_hw_info = { -+ .hw_crc = HWCRC_LEN_3Bytes, -+ .auto_copy = AUTOCOPY_NOSUPPORT, -+ .hw_regs = &hw_reg_addr_info_old_w_isp, - }; - - static struct nvt_ts_hw_info NT36523_hw_info = { -- .carrier_system = 2, -- .hw_crc = 2, -+ .hw_crc = HWCRC_LEN_3Bytes, -+ .auto_copy = CHECK_SPI_DMA_TX_INFO, -+ .hw_regs = &hw_reg_addr_info_old_w_isp, - }; - - static struct nvt_ts_hw_info NT36526_hw_info = { -- .carrier_system = 2, -- .hw_crc = 2, -+ .hw_crc = HWCRC_LEN_3Bytes, -+ .auto_copy = AUTOCOPY_NOSUPPORT, -+ .hw_regs = &hw_reg_addr_info_old_w_isp, - }; - - static struct nvt_ts_hw_info NT36675_hw_info = { -- .carrier_system = 2, -- .hw_crc = 2, -+ .hw_crc = HWCRC_LEN_3Bytes, -+ .auto_copy = AUTOCOPY_NOSUPPORT, -+ .hw_regs = &hw_reg_addr_info_old_w_isp, - }; - - static struct nvt_ts_hw_info NT36672A_hw_info = { -- .carrier_system = 0, -- .hw_crc = 1, -+ .hw_crc = HWCRC_LEN_2Bytes, -+ .auto_copy = AUTOCOPY_NOSUPPORT, -+ .hw_regs = &hw_reg_addr_info_old_w_isp, - }; - - static struct nvt_ts_hw_info NT36772_hw_info = { -- .carrier_system = 0, -- .hw_crc = 0, -+ .hw_crc = HWCRC_NOSUPPORT, -+ .auto_copy = AUTOCOPY_NOSUPPORT, -+ .hw_regs = &hw_reg_addr_info_legacy_w_isp, - }; - - static struct nvt_ts_hw_info NT36525_hw_info = { -- .carrier_system = 0, -- .hw_crc = 0, -+ .hw_crc = HWCRC_NOSUPPORT, -+ .auto_copy = AUTOCOPY_NOSUPPORT, -+ .hw_regs = &hw_reg_addr_info_legacy_w_isp, - }; - - static struct nvt_ts_hw_info NT36676F_hw_info = { -- .carrier_system = 0, -- .hw_crc = 0, -+ .hw_crc = HWCRC_NOSUPPORT, -+ .auto_copy = AUTOCOPY_NOSUPPORT, -+ .hw_regs = &hw_reg_addr_info_legacy_w_isp, - }; - - #define NVT_ID_BYTE_MAX 6 -@@ -329,10 +592,13 @@ struct nvt_ts_trim_id_table { - uint8_t id[NVT_ID_BYTE_MAX]; - uint8_t mask[NVT_ID_BYTE_MAX]; - const struct nvt_ts_mem_map *mmap; -+ const struct nvt_ts_mem_map *mmap_casc; - const struct nvt_ts_hw_info *hwinfo; - }; - - static const struct nvt_ts_trim_id_table trim_id_table[] = { -+ {.id = {0xFF, 0xFF, 0xFF, 0x32, 0x65, 0x03}, .mask = {0, 0, 0, 1, 1, 1}, -+ .mmap = &NT36532_single_memory_map, .mmap_casc = &NT36532_cascade_memory_map, .hwinfo = &NT36532_hw_info}, - {.id = {0x20, 0xFF, 0xFF, 0x23, 0x65, 0x03}, .mask = {1, 0, 0, 1, 1, 1}, - .mmap = &NT36523_memory_map, .hwinfo = &NT36523_hw_info}, - {.id = {0x0C, 0xFF, 0xFF, 0x23, 0x65, 0x03}, .mask = {1, 0, 0, 1, 1, 1}, -- 2.52.0 diff --git a/device/testing/linux-xiaomi-pipa/0010-drivers-media-i2c-ov13b10-add-device-tree-support-an.patch b/device/testing/linux-xiaomi-pipa/0010-drivers-media-i2c-ov13b10-add-device-tree-support-an.patch index 0df7a90e7..bac87fc0a 100644 --- a/device/testing/linux-xiaomi-pipa/0010-drivers-media-i2c-ov13b10-add-device-tree-support-an.patch +++ b/device/testing/linux-xiaomi-pipa/0010-drivers-media-i2c-ov13b10-add-device-tree-support-an.patch @@ -1,4 +1,4 @@ -From c5591f3289e3aaa841af20889ad3d952f88a699b Mon Sep 17 00:00:00 2001 +From b7d4d69d76531e60945f625137a7b266a1447331 Mon Sep 17 00:00:00 2001 From: bluebunny <1812-bluebunny@users.noreply.gitlab.postmarketos.org> Date: Mon, 27 Jan 2025 01:19:39 +0300 Subject: [PATCH 10/12] drivers: media: i2c: ov13b10: add device tree support diff --git a/device/testing/linux-xiaomi-pipa/0011-ASoC-codecs-aw88261-add-hacks-for-xiaomi-pipa.patch b/device/testing/linux-xiaomi-pipa/0011-ASoC-codecs-aw88261-add-hacks-for-xiaomi-pipa.patch index 5912cd5ba..5b0b56781 100644 --- a/device/testing/linux-xiaomi-pipa/0011-ASoC-codecs-aw88261-add-hacks-for-xiaomi-pipa.patch +++ b/device/testing/linux-xiaomi-pipa/0011-ASoC-codecs-aw88261-add-hacks-for-xiaomi-pipa.patch @@ -1,16 +1,18 @@ -From 1876ed85b33282e67f3bf85e97c0920b8fbe7ee3 Mon Sep 17 00:00:00 2001 +From 6e26f796af8264cc0c9f6a6c923e77a0e98e9a72 Mon Sep 17 00:00:00 2001 From: domin746826 Date: Fri, 11 Apr 2025 13:46:25 +0400 Subject: [PATCH 11/12] ASoC: codecs: aw88261: add hacks for xiaomi-pipa aw88261 requires some hacks to work on pipa, including device tree support and non-standard firmware requests to the codec itself. + +The overall hack was reduced, but it still needs rework when linux-next changes land on stable. --- - sound/soc/codecs/aw88261.c | 541 ++++++++++++++++++++----------------- - sound/soc/codecs/aw88261.h | 8 +- - 2 files changed, 297 insertions(+), 252 deletions(-) + sound/soc/codecs/aw88261.c | 210 +++++++++++++++++++++++++++++++++++-- + sound/soc/codecs/aw88261.h | 4 + + 2 files changed, 208 insertions(+), 6 deletions(-) diff --git a/sound/soc/codecs/aw88261.c b/sound/soc/codecs/aw88261.c -index 96b1a85c26aa..8f9770d46517 100644 +index 96b1a85c26aa..f69fb56ec6b0 100644 --- a/sound/soc/codecs/aw88261.c +++ b/sound/soc/codecs/aw88261.c @@ -10,11 +10,13 @@ @@ -27,288 +29,7 @@ index 96b1a85c26aa..8f9770d46517 100644 static const struct regmap_config aw88261_remap_config = { .val_bits = 16, -@@ -29,6 +31,10 @@ static void aw88261_dev_set_volume(struct aw_device *aw_dev, unsigned int value) - struct aw_volume_desc *vol_desc = &aw_dev->volume_desc; - unsigned int real_value, volume; - unsigned int reg_value; -+ unsigned int volume_boost = 3; // Apply a 3dB boost to all volume settings -+ -+ /* Apply boosted volume - increase output level for Xiaomi Pad 6 */ -+ value = (value > volume_boost) ? (value - volume_boost) : 0; - - volume = min((value + vol_desc->init_volume), (unsigned int)AW88261_MUTE_VOL); - real_value = DB_TO_REG_VAL(volume); -@@ -37,7 +43,7 @@ static void aw88261_dev_set_volume(struct aw_device *aw_dev, unsigned int value) - - real_value = (real_value | (reg_value & AW88261_VOL_START_MASK)); - -- dev_dbg(aw_dev->dev, "value 0x%x , real_value:0x%x", value, real_value); -+ dev_dbg(aw_dev->dev, "value 0x%x , real_value:0x%x (boosted)", value, real_value); - - regmap_write(aw_dev->regmap, AW88261_SYSCTRL2_REG, real_value); - } -@@ -88,12 +94,12 @@ static void aw88261_dev_fade_out(struct aw_device *aw_dev) - - static void aw88261_dev_i2s_tx_enable(struct aw_device *aw_dev, bool flag) - { -- if (flag) -- regmap_update_bits(aw_dev->regmap, AW88261_I2SCFG1_REG, -- ~AW88261_I2STXEN_MASK, AW88261_I2STXEN_ENABLE_VALUE); -- else -- regmap_update_bits(aw_dev->regmap, AW88261_I2SCFG1_REG, -- ~AW88261_I2STXEN_MASK, AW88261_I2STXEN_DISABLE_VALUE); -+ // if (flag) -+ // regmap_update_bits(aw_dev->regmap, AW88261_I2SCFG1_REG, -+ // ~AW88261_I2STXEN_MASK, AW88261_I2STXEN_ENABLE_VALUE); -+ // else -+ // regmap_update_bits(aw_dev->regmap, AW88261_I2SCFG1_REG, -+ // ~AW88261_I2STXEN_MASK, AW88261_I2STXEN_DISABLE_VALUE); - } - - static void aw88261_dev_pwd(struct aw_device *aw_dev, bool pwd) -@@ -108,11 +114,12 @@ static void aw88261_dev_pwd(struct aw_device *aw_dev, bool pwd) - - static void aw88261_dev_amppd(struct aw_device *aw_dev, bool amppd) - { -+ int ret; - if (amppd) -- regmap_update_bits(aw_dev->regmap, AW88261_SYSCTRL_REG, -+ ret = regmap_update_bits(aw_dev->regmap, AW88261_SYSCTRL_REG, - ~AW88261_AMPPD_MASK, AW88261_AMPPD_POWER_DOWN_VALUE); - else -- regmap_update_bits(aw_dev->regmap, AW88261_SYSCTRL_REG, -+ ret = regmap_update_bits(aw_dev->regmap, AW88261_SYSCTRL_REG, - ~AW88261_AMPPD_MASK, AW88261_AMPPD_WORKING_VALUE); - } - -@@ -149,11 +156,19 @@ static int aw88261_dev_get_iis_status(struct aw_device *aw_dev) - ret = regmap_read(aw_dev->regmap, AW88261_SYSST_REG, ®_val); - if (ret) - return ret; -- if ((reg_val & AW88261_BIT_PLL_CHECK) != AW88261_BIT_PLL_CHECK) { -- dev_err(aw_dev->dev, "check pll lock fail,reg_val:0x%04x", reg_val); -- return -EINVAL; -- } - -+ bool pll_lock = (reg_val & (1 << 0)) == 0x0001; -+ bool clks_available = (reg_val & (1 << 5)) == 0x0000; -+ -+ if (pll_lock && clks_available) { -+ dev_dbg(aw_dev->dev, "IIS signal is OK"); -+ ret = 0; -+ } else { -+ dev_err(aw_dev->dev, -+ "IIS signal is not OK, pll_lock:%d, clks_available:%d", -+ pll_lock, clks_available); -+ ret = -EINVAL; -+ } - return ret; - } - -@@ -174,68 +189,27 @@ static int aw88261_dev_check_mode1_pll(struct aw_device *aw_dev) - return -EPERM; - } - --static int aw88261_dev_check_mode2_pll(struct aw_device *aw_dev) -+static int aw88261_dev_check_syspll(struct aw_device *aw_dev) - { -- unsigned int reg_val; -- int ret, i; -- -- ret = regmap_read(aw_dev->regmap, AW88261_PLLCTRL1_REG, ®_val); -- if (ret) -- return ret; -- -- reg_val &= (~AW88261_CCO_MUX_MASK); -- if (reg_val == AW88261_CCO_MUX_DIVIDED_VALUE) { -- dev_dbg(aw_dev->dev, "CCO_MUX is already divider"); -- return -EPERM; -- } -- -- /* change mode2 */ -- ret = regmap_update_bits(aw_dev->regmap, AW88261_PLLCTRL1_REG, -- ~AW88261_CCO_MUX_MASK, AW88261_CCO_MUX_DIVIDED_VALUE); -- if (ret) -- return ret; -- -- for (i = 0; i < AW88261_DEV_SYSST_CHECK_MAX; i++) { -- ret = aw88261_dev_get_iis_status(aw_dev); -- if (ret) { -- dev_err(aw_dev->dev, "mode2 iis signal check error"); -- usleep_range(AW88261_2000_US, AW88261_2000_US + 10); -- } else { -+ int ret; -+ int retry_count = 0; -+ const int max_retries = 20; // Increase retries for PLL stabilization -+ -+ while (retry_count < max_retries) { -+ ret = aw88261_dev_check_mode1_pll(aw_dev); -+ if (ret != 0) -+ retry_count++; -+ else - break; -- } - } - -- /* change mode1 */ -- ret = regmap_update_bits(aw_dev->regmap, AW88261_PLLCTRL1_REG, -- ~AW88261_CCO_MUX_MASK, AW88261_CCO_MUX_BYPASS_VALUE); -- if (ret == 0) { -- usleep_range(AW88261_2000_US, AW88261_2000_US + 10); -- for (i = 0; i < AW88261_DEV_SYSST_CHECK_MAX; i++) { -- ret = aw88261_dev_check_mode1_pll(aw_dev); -- if (ret) { -- dev_err(aw_dev->dev, "mode2 switch to mode1, iis signal check error"); -- usleep_range(AW88261_2000_US, AW88261_2000_US + 10); -- } else { -- break; -- } -- } -+ if (retry_count == max_retries) { -+ dev_err(aw_dev->dev, -+ "Failed to stabilize PLL after %d attempts, we're cooked", max_retries); -+ return -ETIMEDOUT; - } -- -- return ret; --} -- --static int aw88261_dev_check_syspll(struct aw_device *aw_dev) --{ -- int ret; -- -- ret = aw88261_dev_check_mode1_pll(aw_dev); -- if (ret) { -- dev_dbg(aw_dev->dev, "mode1 check iis failed try switch to mode2 check"); -- ret = aw88261_dev_check_mode2_pll(aw_dev); -- if (ret) { -- dev_err(aw_dev->dev, "mode2 check iis failed"); -- return ret; -- } -+ if (ret == 0) { -+ dev_info(aw_dev->dev, "PLL stabilized successfully"); - } - - return ret; -@@ -278,123 +252,13 @@ static void aw88261_dev_uls_hmute(struct aw_device *aw_dev, bool uls_hmute) - AW88261_ULS_HMUTE_DISABLE_VALUE); - } - --static void aw88261_reg_force_set(struct aw88261 *aw88261) --{ -- if (aw88261->frcset_en == AW88261_FRCSET_ENABLE) { -- /* set FORCE_PWM */ -- regmap_update_bits(aw88261->regmap, AW88261_BSTCTRL3_REG, -- AW88261_FORCE_PWM_MASK, AW88261_FORCE_PWM_FORCEMINUS_PWM_VALUE); -- /* set BOOST_OS_WIDTH */ -- regmap_update_bits(aw88261->regmap, AW88261_BSTCTRL5_REG, -- AW88261_BST_OS_WIDTH_MASK, AW88261_BST_OS_WIDTH_50NS_VALUE); -- /* set BURST_LOOPR */ -- regmap_update_bits(aw88261->regmap, AW88261_BSTCTRL6_REG, -- AW88261_BST_LOOPR_MASK, AW88261_BST_LOOPR_340K_VALUE); -- /* set RSQN_DLY */ -- regmap_update_bits(aw88261->regmap, AW88261_BSTCTRL7_REG, -- AW88261_RSQN_DLY_MASK, AW88261_RSQN_DLY_35NS_VALUE); -- /* set BURST_SSMODE */ -- regmap_update_bits(aw88261->regmap, AW88261_BSTCTRL8_REG, -- AW88261_BURST_SSMODE_MASK, AW88261_BURST_SSMODE_FAST_VALUE); -- /* set BST_BURST */ -- regmap_update_bits(aw88261->regmap, AW88261_BSTCTRL9_REG, -- AW88261_BST_BURST_MASK, AW88261_BST_BURST_30MA_VALUE); -- } else { -- dev_dbg(aw88261->aw_pa->dev, "needn't set reg value"); -- } --} -- --static int aw88261_dev_get_icalk(struct aw_device *aw_dev, int16_t *icalk) --{ -- u16 reg_icalk, reg_icalkl; -- unsigned int reg_val; -- int ret; -- -- ret = regmap_read(aw_dev->regmap, AW88261_EFRH4_REG, ®_val); -- if (ret) -- return ret; -- -- reg_icalk = reg_val & (~AW88261_EF_ISN_GESLP_H_MASK); -- -- ret = regmap_read(aw_dev->regmap, AW88261_EFRL4_REG, ®_val); -- if (ret) -- return ret; -- -- reg_icalkl = reg_val & (~AW88261_EF_ISN_GESLP_L_MASK); -- -- reg_icalk = (reg_icalk >> AW88261_ICALK_SHIFT) & (reg_icalkl >> AW88261_ICALKL_SHIFT); -- -- if (reg_icalk & (~AW88261_EF_ISN_GESLP_SIGN_MASK)) -- reg_icalk = reg_icalk | ~AW88261_EF_ISN_GESLP_NEG; -- -- *icalk = (int16_t)reg_icalk; -- -- return ret; --} -- --static int aw88261_dev_get_vcalk(struct aw_device *aw_dev, int16_t *vcalk) --{ -- u16 reg_vcalk, reg_vcalkl; -- unsigned int reg_val; -- int ret; -- -- ret = regmap_read(aw_dev->regmap, AW88261_EFRH3_REG, ®_val); -- if (ret) -- return ret; -- -- reg_vcalk = (u16)reg_val & (~AW88261_EF_VSN_GESLP_H_MASK); -- -- ret = regmap_read(aw_dev->regmap, AW88261_EFRL3_REG, ®_val); -- if (ret) -- return ret; -- -- reg_vcalkl = (u16)reg_val & (~AW88261_EF_VSN_GESLP_L_MASK); -- -- reg_vcalk = (reg_vcalk >> AW88261_VCALK_SHIFT) & (reg_vcalkl >> AW88261_VCALKL_SHIFT); -- -- if (reg_vcalk & AW88261_EF_VSN_GESLP_SIGN_MASK) -- reg_vcalk = reg_vcalk | (~AW88261_EF_VSN_GESLP_NEG); -- *vcalk = (int16_t)reg_vcalk; -- -- return ret; --} -- --static int aw88261_dev_set_vcalb(struct aw_device *aw_dev) --{ -- int16_t icalk_val, vcalk_val; -- int icalk, vcalk, vcalb; -- u32 reg_val; -- int ret; -- -- ret = aw88261_dev_get_icalk(aw_dev, &icalk_val); -- if (ret) -- return ret; -- -- ret = aw88261_dev_get_vcalk(aw_dev, &vcalk_val); -- if (ret) -- return ret; -- -- icalk = AW88261_CABL_BASE_VALUE + AW88261_ICABLK_FACTOR * icalk_val; -- vcalk = AW88261_CABL_BASE_VALUE + AW88261_VCABLK_FACTOR * vcalk_val; -- if (!vcalk) -- return -EINVAL; -- -- vcalb = AW88261_VCAL_FACTOR * icalk / vcalk; -- reg_val = (unsigned int)vcalb; -- -- dev_dbg(aw_dev->dev, "icalk=%d, vcalk=%d, vcalb=%d, reg_val=0x%04x", -- icalk, vcalk, vcalb, reg_val); -- ret = regmap_write(aw_dev->regmap, AW88261_VSNTM1_REG, reg_val); -- -- return ret; --} -- --static int aw88261_dev_reg_update(struct aw88261 *aw88261, -- unsigned char *data, unsigned int len) -+static int aw88261_dev_reg_update(struct aw88261 *aw88261, unsigned char *data, unsigned int len) - { +@@ -395,6 +397,8 @@ static int aw88261_dev_reg_update(struct aw88261 *aw88261, struct aw_device *aw_dev = aw88261->aw_pa; struct aw_volume_desc *vol_desc = &aw_dev->volume_desc; unsigned int read_val, efcheck_val, read_vol; @@ -317,7 +38,7 @@ index 96b1a85c26aa..8f9770d46517 100644 int data_len, i, ret; int16_t *reg_data; u16 reg_val; -@@ -417,6 +281,31 @@ static int aw88261_dev_reg_update(struct aw88261 *aw88261, +@@ -417,6 +421,31 @@ static int aw88261_dev_reg_update(struct aw88261 *aw88261, reg_addr = reg_data[i]; reg_val = reg_data[i + 1]; @@ -349,20 +70,10 @@ index 96b1a85c26aa..8f9770d46517 100644 if (reg_addr == AW88261_SYSCTRL_REG) { aw88261->amppd_st = reg_val & (~AW88261_AMPPD_MASK); ret = regmap_read(aw_dev->regmap, reg_addr, &read_val); -@@ -432,21 +321,45 @@ static int aw88261_dev_reg_update(struct aw88261 *aw88261, - /* enable uls hmute */ - reg_val &= AW88261_ULS_HMUTE_MASK; - reg_val |= AW88261_ULS_HMUTE_ENABLE_VALUE; -+ -+ reg_val = 0b0011001001000000; +@@ -442,6 +471,35 @@ static int aw88261_dev_reg_update(struct aw88261 *aw88261, + aw88261->efuse_check = AW88261_EF_AND_CHECK; } -- if (reg_addr == AW88261_DBGCTRL_REG) { -- efcheck_val = reg_val & (~AW88261_EF_DBMD_MASK); -- if (efcheck_val == AW88261_OR_VALUE) -- aw88261->efuse_check = AW88261_EF_OR_CHECK; -- else -- aw88261->efuse_check = AW88261_EF_AND_CHECK; + /* Special handling for I2SCTRL registers for Xiaomi Pad 6 */ + if (reg_addr == AW88261_I2SCTRL1_REG && + (of_machine_is_compatible("xiaomi,pipa") || @@ -390,57 +101,12 @@ index 96b1a85c26aa..8f9770d46517 100644 + aw_dev->dev, + "Setting TDM mode for Xiaomi Pad 6, channel: %d", + slot_num); - } - ++ } ++ /* i2stxen */ if (reg_addr == AW88261_I2SCTRL3_REG) { /* close tx */ -- reg_val &= AW88261_I2STXEN_MASK; -- reg_val |= AW88261_I2STXEN_DISABLE_VALUE; -+ // reg_val &= AW88261_I2STXEN_MASK; -+ // reg_val |= AW88261_I2STXEN_DISABLE_VALUE; -+ reg_val = 0b0000000011110110; // 0b00000000_0_0_0_1_0_0_1_0; - } - - if (reg_addr == AW88261_SYSCTRL2_REG) { -@@ -456,18 +369,11 @@ static int aw88261_dev_reg_update(struct aw88261 *aw88261, - REG_VAL_TO_DB(read_vol); - } - -- if (reg_addr == AW88261_VSNTM1_REG) -- continue; -- - ret = regmap_write(aw_dev->regmap, reg_addr, reg_val); - if (ret) - break; - } - -- ret = aw88261_dev_set_vcalb(aw_dev); -- if (ret) -- return ret; -- - if (aw_dev->prof_cur != aw_dev->prof_index) - vol_desc->ctl_volume = 0; - -@@ -580,8 +486,6 @@ static int aw88261_dev_start(struct aw88261 *aw88261) - if (aw88261->amppd_st) - aw88261_dev_amppd(aw_dev, true); - -- aw88261_reg_force_set(aw88261); -- - /* close uls mute */ - aw88261_dev_uls_hmute(aw_dev, false); - -@@ -609,7 +513,7 @@ static int aw88261_dev_start(struct aw88261 *aw88261) - static int aw88261_dev_stop(struct aw_device *aw_dev) - { - if (aw_dev->status == AW88261_DEV_PW_OFF) { -- dev_info(aw_dev->dev, "already power off"); -+ dev_dbg(aw_dev->dev, "already power off"); - return 0; - } - -@@ -711,6 +615,86 @@ static void aw88261_start(struct aw88261 *aw88261, bool sync_start) +@@ -711,6 +769,70 @@ static void aw88261_start(struct aw88261 *aw88261, bool sync_start) AW88261_START_WORK_DELAY_MS); } @@ -501,23 +167,7 @@ index 96b1a85c26aa..8f9770d46517 100644 + return 0; +} + -+static int aw88261_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) -+{ -+ // aw_snd_soc_codec_t *codec = dai->component; -+ -+ // struct aw88261 *aw88261 = snd_soc_component_get_drvdata(codec); -+ -+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { -+ // handle playback -+ } else { -+ // handle capture -+ } -+ -+ return 0; -+} -+ +static const struct snd_soc_dai_ops aw88261_dai_ops = { -+ .startup = aw88261_startup, + .set_stream = aw88261_dai_set_stream, + .set_sysclk = aw88261_dai_set_sysclk, + .set_fmt = aw88261_dai_set_fmt, @@ -527,20 +177,7 @@ index 96b1a85c26aa..8f9770d46517 100644 static struct snd_soc_dai_driver aw88261_dai[] = { { .name = "aw88261-aif", -@@ -718,17 +702,18 @@ static struct snd_soc_dai_driver aw88261_dai[] = { - .playback = { - .stream_name = "Speaker_Playback", - .channels_min = 1, -- .channels_max = 2, -+ .channels_max = 1, - .rates = AW88261_RATES, - .formats = AW88261_FORMATS, - }, - .capture = { - .stream_name = "Speaker_Capture", - .channels_min = 1, -- .channels_max = 2, -+ .channels_max = 1, +@@ -729,6 +851,7 @@ static struct snd_soc_dai_driver aw88261_dai[] = { .rates = AW88261_RATES, .formats = AW88261_FORMATS, }, @@ -548,7 +185,7 @@ index 96b1a85c26aa..8f9770d46517 100644 }, }; -@@ -956,6 +941,25 @@ static int aw88261_set_fade_step(struct snd_kcontrol *kcontrol, +@@ -956,6 +1079,25 @@ static int aw88261_set_fade_step(struct snd_kcontrol *kcontrol, return 0; } @@ -574,59 +211,7 @@ index 96b1a85c26aa..8f9770d46517 100644 static const struct snd_kcontrol_new aw88261_controls[] = { SOC_SINGLE_EXT("PCM Playback Volume", AW88261_SYSCTRL2_REG, 6, AW88261_MUTE_VOL, 0, aw88261_volume_get, -@@ -1009,38 +1013,6 @@ static const struct snd_soc_dapm_route aw88261_audio_map[] = { - {"AIF_TX", NULL, "ADC Input"}, - }; - --static int aw88261_frcset_check(struct aw88261 *aw88261) --{ -- unsigned int reg_val; -- u16 temh, teml, tem; -- int ret; -- -- ret = regmap_read(aw88261->regmap, AW88261_EFRH3_REG, ®_val); -- if (ret) -- return ret; -- temh = ((u16)reg_val & (~AW88261_TEMH_MASK)); -- -- ret = regmap_read(aw88261->regmap, AW88261_EFRL3_REG, ®_val); -- if (ret) -- return ret; -- teml = ((u16)reg_val & (~AW88261_TEML_MASK)); -- -- if (aw88261->efuse_check == AW88261_EF_OR_CHECK) -- tem = (temh | teml); -- else -- tem = (temh & teml); -- -- if (tem == AW88261_DEFAULT_CFG) -- aw88261->frcset_en = AW88261_FRCSET_ENABLE; -- else -- aw88261->frcset_en = AW88261_FRCSET_DISABLE; -- -- dev_dbg(aw88261->aw_pa->dev, "tem is 0x%04x, frcset_en is %d", -- tem, aw88261->frcset_en); -- -- return ret; --} -- - static int aw88261_dev_init(struct aw88261 *aw88261, struct aw_container *aw_cfg) - { - struct aw_device *aw_dev = aw88261->aw_pa; -@@ -1067,12 +1039,6 @@ static int aw88261_dev_init(struct aw88261 *aw88261, struct aw_container *aw_cfg - return ret; - } - -- ret = aw88261_frcset_check(aw88261); -- if (ret) { -- dev_err(aw_dev->dev, "aw88261_frcset_check ret = %d\n", ret); -- return ret; -- } -- - aw88261_dev_clear_int_status(aw_dev); - - aw88261_dev_uls_hmute(aw_dev, true); -@@ -1097,13 +1063,13 @@ static int aw88261_request_firmware_file(struct aw88261 *aw88261) +@@ -1097,13 +1239,13 @@ static int aw88261_request_firmware_file(struct aw88261 *aw88261) aw88261->aw_pa->fw_status = AW88261_DEV_FW_FAILED; @@ -643,7 +228,7 @@ index 96b1a85c26aa..8f9770d46517 100644 aw88261->aw_cfg = devm_kzalloc(aw88261->aw_pa->dev, cont->size + sizeof(int), GFP_KERNEL); if (!aw88261->aw_cfg) { -@@ -1116,7 +1082,7 @@ static int aw88261_request_firmware_file(struct aw88261 *aw88261) +@@ -1116,7 +1258,7 @@ static int aw88261_request_firmware_file(struct aw88261 *aw88261) ret = aw88395_dev_load_acf_check(aw88261->aw_pa, aw88261->aw_cfg); if (ret) { @@ -652,7 +237,7 @@ index 96b1a85c26aa..8f9770d46517 100644 return ret; } -@@ -1135,28 +1101,65 @@ static int aw88261_codec_probe(struct snd_soc_component *component) +@@ -1135,6 +1277,10 @@ static int aw88261_codec_probe(struct snd_soc_component *component) struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); struct aw88261 *aw88261 = snd_soc_component_get_drvdata(component); int ret; @@ -663,30 +248,7 @@ index 96b1a85c26aa..8f9770d46517 100644 INIT_DELAYED_WORK(&aw88261->start_work, aw88261_startup_work); -+ /* Log device info for debugging */ -+ dev_info(component->dev, -+ "Probing AW88261 codec for Xiaomi Pad 6 (channel %d)", -+ aw88261->aw_pa->channel); -+ - ret = aw88261_request_firmware_file(aw88261); - if (ret) - return dev_err_probe(aw88261->aw_pa->dev, ret, - "aw88261_request_firmware_file failed\n"); - -- /* add widgets */ -+ /* add widgets with unique names for each channel */ - ret = snd_soc_dapm_new_controls(dapm, aw88261_dapm_widgets, - ARRAY_SIZE(aw88261_dapm_widgets)); -+ dev_info(component->dev, "Widget return status: %d\n", ret); - if (ret) - return ret; - -- /* add route */ -+ /* add route with unique widget names */ -+ - ret = snd_soc_dapm_add_routes(dapm, aw88261_audio_map, - ARRAY_SIZE(aw88261_audio_map)); -+ dev_info(component->dev, "Route return status: %d\n", ret); +@@ -1155,8 +1301,24 @@ static int aw88261_codec_probe(struct snd_soc_component *component) if (ret) return ret; @@ -709,20 +271,11 @@ index 96b1a85c26aa..8f9770d46517 100644 + if (ret) { + dev_err(component->dev, "Failed to add controls: %d\n", ret); + return ret; -+ } -+ -+ /* Apply Xiaomi Pad 6 specific optimizations */ -+ if (of_machine_is_compatible("xiaomi,pipa") || -+ of_machine_is_compatible("qcom,sm8250-mtp")) { -+ dev_info( -+ component->dev, -+ "Applying Xiaomi Pad 6 specific optimizations for channel %d", -+ aw88261->aw_pa->channel); + } return ret; } -@@ -1173,6 +1176,14 @@ static const struct snd_soc_component_driver soc_codec_dev_aw88261 = { +@@ -1173,6 +1335,14 @@ static const struct snd_soc_component_driver soc_codec_dev_aw88261 = { .remove = aw88261_codec_remove, }; @@ -737,7 +290,7 @@ index 96b1a85c26aa..8f9770d46517 100644 static void aw88261_parse_channel_dt(struct aw88261 *aw88261) { struct aw_device *aw_dev = aw88261->aw_pa; -@@ -1185,6 +1196,19 @@ static void aw88261_parse_channel_dt(struct aw88261 *aw88261) +@@ -1185,6 +1355,19 @@ static void aw88261_parse_channel_dt(struct aw88261 *aw88261) aw_dev->channel = channel_value; } @@ -757,13 +310,7 @@ index 96b1a85c26aa..8f9770d46517 100644 static int aw88261_init(struct aw88261 *aw88261, struct i2c_client *i2c, struct regmap *regmap) { struct aw_device *aw_dev; -@@ -1218,11 +1242,12 @@ static int aw88261_init(struct aw88261 *aw88261, struct i2c_client *i2c, struct - aw_dev->prof_info.count = 0; - aw_dev->prof_info.prof_type = AW88395_DEV_NONE_TYPE_ID; - aw_dev->channel = 0; -- aw_dev->fw_status = AW88261_DEV_FW_FAILED; -+ aw_dev->fw_status = AW88261_DEV_FW_OK; - aw_dev->fade_step = AW88261_VOLUME_STEP_DB; +@@ -1223,6 +1406,7 @@ static int aw88261_init(struct aw88261 *aw88261, struct i2c_client *i2c, struct aw_dev->volume_desc.ctl_volume = AW88261_VOL_DEFAULT_VALUE; aw_dev->volume_desc.mute_volume = AW88261_MUTE_VOL; aw88261_parse_channel_dt(aw88261); @@ -771,16 +318,7 @@ index 96b1a85c26aa..8f9770d46517 100644 return ret; } -@@ -1232,6 +1257,8 @@ static int aw88261_i2c_probe(struct i2c_client *i2c) - struct aw88261 *aw88261; - int ret; - -+ dev_info(&i2c->dev, "Probing AW88261 at address 0x%x, name: %s\n", -+ i2c->addr, dev_name(&i2c->dev)); - ret = i2c_check_functionality(i2c->adapter, I2C_FUNC_I2C); - if (!ret) - return dev_err_probe(&i2c->dev, -ENXIO, "check_functionality failed"); -@@ -1244,6 +1271,13 @@ static int aw88261_i2c_probe(struct i2c_client *i2c) +@@ -1244,6 +1428,13 @@ static int aw88261_i2c_probe(struct i2c_client *i2c) i2c_set_clientdata(i2c, aw88261); @@ -794,7 +332,7 @@ index 96b1a85c26aa..8f9770d46517 100644 aw88261->regmap = devm_regmap_init_i2c(i2c, &aw88261_remap_config); if (IS_ERR(aw88261->regmap)) { ret = PTR_ERR(aw88261->regmap); -@@ -1270,9 +1304,16 @@ static const struct i2c_device_id aw88261_i2c_id[] = { +@@ -1270,9 +1461,16 @@ static const struct i2c_device_id aw88261_i2c_id[] = { }; MODULE_DEVICE_TABLE(i2c, aw88261_i2c_id); @@ -812,36 +350,27 @@ index 96b1a85c26aa..8f9770d46517 100644 .probe = aw88261_i2c_probe, .id_table = aw88261_i2c_id, diff --git a/sound/soc/codecs/aw88261.h b/sound/soc/codecs/aw88261.h -index 734d0f93ced9..4cfa84c1b3f3 100644 +index 734d0f93ced9..c62043ed5e07 100644 --- a/sound/soc/codecs/aw88261.h +++ b/sound/soc/codecs/aw88261.h -@@ -372,8 +372,8 @@ +@@ -374,6 +374,7 @@ - #define AW88261_I2C_NAME "aw88261" - --#define AW88261_RATES (SNDRV_PCM_RATE_8000_48000 | \ -- SNDRV_PCM_RATE_96000) -+#define AW88261_RATES SNDRV_PCM_RATE_48000 + #define AW88261_RATES (SNDRV_PCM_RATE_8000_48000 | \ + SNDRV_PCM_RATE_96000) + #define AW88261_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ SNDRV_PCM_FMTBIT_S24_LE | \ SNDRV_PCM_FMTBIT_S32_LE) -@@ -448,11 +448,15 @@ struct aw88261 { +@@ -448,6 +449,9 @@ struct aw88261 { struct regmap *regmap; struct aw_container *aw_cfg; + const char *fw_name; ++ int sysclk; + int efuse_check; int frcset_en; unsigned int mute_st; - unsigned int amppd_st; - -+ int sysclk; -+ - bool phase_sync; - }; - -- 2.52.0 diff --git a/device/testing/linux-xiaomi-pipa/0012-ASoC-qcom-sm8250-Add-tdm-support.patch b/device/testing/linux-xiaomi-pipa/0012-ASoC-qcom-sm8250-Add-tdm-support.patch index 798486789..a417bce07 100644 --- a/device/testing/linux-xiaomi-pipa/0012-ASoC-qcom-sm8250-Add-tdm-support.patch +++ b/device/testing/linux-xiaomi-pipa/0012-ASoC-qcom-sm8250-Add-tdm-support.patch @@ -1,4 +1,4 @@ -From c07e80d775c574391b70bec855075ba305fd0e78 Mon Sep 17 00:00:00 2001 +From ec0d4317e6e0c57f64aa9a175b827f21c2a208a5 Mon Sep 17 00:00:00 2001 From: Jianhua Lu Date: Mon, 11 Dec 2023 09:23:28 +0800 Subject: [PATCH 12/12] ASoC: qcom: sm8250: Add tdm support diff --git a/device/testing/linux-xiaomi-pipa/APKBUILD b/device/testing/linux-xiaomi-pipa/APKBUILD index 622d84a1d..426b3677e 100644 --- a/device/testing/linux-xiaomi-pipa/APKBUILD +++ b/device/testing/linux-xiaomi-pipa/APKBUILD @@ -1,7 +1,7 @@ maintainer="bluebunny " _flavor="xiaomi-pipa" pkgname=linux-$_flavor -pkgver=6.19.10 +pkgver=6.19.11 pkgrel=0 pkgdesc="Stable kernel for Xiaomi Pad 6" arch="aarch64" @@ -90,18 +90,18 @@ package() { } sha512sums=" -11a397c54dddf02fc62b52b2571a0d13cf96450c2e67cffa759c34b9432e51dcb39871347c9cdbca36cfaf78198015d8d7a4d2c2a8d506e22b998fd2b185341b linux-6.19.10.tar.xz -1fa160c966de44287af79d33bda865abe8023e86756f1a6bb1bb01f30b264cbd52e6ae2c9bf24d77689cfb94eb5949d7a8049c20f222b8d34b63e6d2b72cfdba config-xiaomi-pipa.aarch64 -b074e307a6d670d4e07e21fef8a10a17d19b3f7c42d0c13c862c0411d36463e897d4351b7db6238fcd3c79d455a1716bd63be42d41158dadf91529cbac96433a 0001-arm64-dts-qcom-sm8250-xiaomi-pipa-Add-device-tree-fo.patch -6ebbe90abac86eed17e3c8c162ff3d161422d8a5a8359de75ace7482ff73cfbc01e50b116d4d1753e1e889b3bf6baf10e7f90e5964cd6e88e399f2f53f802154 0002-power-supply-Add-driver-for-Qualcomm-PMIC-fuel-gauge.patch -4602990473e9f4c446b62a1db80f23631542f29427847ae6eace5d8da0615e49443438d2a934530388b1d236c9d489d869136f2fc2469756e20d5eaa88861eb9 0003-power-supply-add-bq25970-charger-driver.patch -06975736172a08bae8354bf1e5f958224454510829fa339e7e0318a2cea78aef84aea71856d563ee8ae1f734ab174db2897a9236f46c75b7f120dadce749bb3b 0004-Input-Add-nt36523-touchscreen-driver.patch -488ca6bf65f07a0876d8362aa56422af77cc9e6aa421be7ffc3425886549c97857597d6915880a0851e88b844c132c3b57958fa911ef4d26c8be0479d71239ea 0005-drm-Add-drm-notifier-support.patch -3f3d6825a06a2eacc1297c3857102550701d12cf6530f65b099b11ce0803d4148127223a8552417f0757618d82d671251d44c3b665af55b856c04ae5c92e098b 0006-drm-dsi-emit-panel-turn-on-off-signal-to-touchscreen.patch -47968c31e40229f555ce31cd3674a00841b1feec9b30cbd3724415384965207e59d9b998ee59dbaccb73b431666b0071cf5f589bd63e841743d14ea4926f7432 0007-drm-msm-dsi-change-sync-mode-to-sync-on-DSI0-rather-.patch -959c6ee7640887db16f6d0e8722daacff1ecab61d4146c60922129d154a96174559eef2819f46f6771b38704f63cbb9de08c1e57bcc8b292054592efa323710e 0008-drm-msm-dsi-support-DSC-configurations-with-slice_pe.patch -6613e4c6c7ec2619a4d9440546852ac3edaf55a1f10011c99a339354162fee91858d8cf4b8367a65579a789cbfa2d10e81f4fe28ebefde6275de76a0a087e99e 0009-drm-panel-Add-support-for-Novatek-NT36532-panel.patch -52c7bf7a788c47924fdc8f6d0a667fa89dbc9c7f1d87a71ba313866a0046832d573fc2acb132644d6a3d09022efd05cac096cc8741a2c16450755c43249766f4 0010-drivers-media-i2c-ov13b10-add-device-tree-support-an.patch -5b0204da89898145d6ed1d3a60c35a9b3c5ba319e883ddc30c685daa427558702795a7a86a84ecb0a167791d951b1f5e3cd402ad9636b528111ac3c79805396f 0011-ASoC-codecs-aw88261-add-hacks-for-xiaomi-pipa.patch -569377adb477d233b88b7b922d924d781a78e91ab829afe03e3a22882bc7b852e4dc6e34ea299e1e7a53e759a71c8c9e763e8e1dbf3e7e1fe1b0ea3f38b02cb9 0012-ASoC-qcom-sm8250-Add-tdm-support.patch +d458fdf65f08b501978d1e274c777633b8473628fb099e2a9a8aac3a943b157fa5132a8ec026cc242f836eb2c441701b5e342f30402d10b12f6759097775de2a linux-6.19.11.tar.xz +21638c8ad6858257885ccc78c4fb81937986f4b6e4a496bb5cfee19e642d06604209c757de96b0d1cc9ff54f66ecaabc69d68971651b31f6192a5ca7ab0214d5 config-xiaomi-pipa.aarch64 +d0758c5d4d4be8812fcbb10c60cc69f86dfd6cd0c305840cb1d445eea7999ee2e68c7a2211869426d2f25cc4b1a5ada5a16d02abf49d31929d6522b40446faa6 0001-arm64-dts-qcom-sm8250-xiaomi-pipa-Add-device-tree-fo.patch +7e69dba0cfb93ed6f6cfcc7a5b4a9fe5b54c2b5a93a39a05b97928f4de9f1acc3780fb4668310548acc294649e135cdccb7ba5c7c4133286c69ab84e26c9e8ff 0002-power-supply-Add-driver-for-Qualcomm-PMIC-fuel-gauge.patch +20a2c5424179dc625ff5d6f733ecf77fe5fd1388373f6a1c637d0324b5ddd738817e5bec4be0409e2073c907547b533b88982049f145f1c2261e246f998d7043 0003-power-supply-add-bq25970-charger-driver.patch +c9ee1043db813789312f93de40f1cd281025b6abb7afed9410403db1e9422922e2c3c7ebeeb29b7cb43516fa8eb265165d2c2f3895c5ef1cff16b7100f7289b7 0004-Input-Add-nt36523-touchscreen-driver.patch +a89109d1cedec7288c71b1966a78e73572fef98a6ec06654ea787833a442f5f5e368d6793060a78262a54abaad59c6f503b23622762cefcac0c5d0bb2f449abd 0005-drm-Add-drm-notifier-support.patch +18bf12f551b0b0dc78f29f3e0a0a7f01bb02ca425987ef338cee270d0833e33d4a22e0d1b2465d5089581e94a5c959efbee35f9b40fa67c4d110e21690525811 0006-drm-dsi-emit-panel-turn-on-off-signal-to-touchscreen.patch +a3989290372f0460a4ddde37f4ff6ad16dab34706b0723f1f60e01cd59792c11f59ccd1bc083b5f24f35138eaccc07b00ca7ace970c65fd2eb9dabbef7b1506f 0007-drm-msm-dsi-change-sync-mode-to-sync-on-DSI0-rather-.patch +2a6d83c12a7958d3b53980de7d6202e2eb80134cd203cd809142f245ccf1d33ff0f07f6b110bf8bd2109e26744a0ee61e628be0d275fc722cbb8224d64abbba3 0008-drm-msm-dsi-support-DSC-configurations-with-slice_pe.patch +65306c9462f3a4cc20f09ca6abede22e1b3948856181f8014c1fd3e4c2dcb44598c1899a4e7241a8eb055797ac3796d87cb6476581fd9fc478e91b0ea8014f5b 0009-drm-panel-Add-support-for-Novatek-NT36532-panel.patch +becec854853aa2b21545b4132c024524f185cd6a63f816361dc970ae6635068430ec78b74fb08f7cc4bcdb92facc8596de78e5a1072f68f38c19e6d0f3d513de 0010-drivers-media-i2c-ov13b10-add-device-tree-support-an.patch +f3487b392bab9158878b8354a133c8f7868b0b61791f2c189e8c6d615f970af8c81c475e6dba82c48451df0c3a15fe0c7cc2e1f8d2a7b8dd69319b9f3bbd35ce 0011-ASoC-codecs-aw88261-add-hacks-for-xiaomi-pipa.patch +4863893049b002352144b7935929cbb89f0b2253735efb4aab96f9e18c7834e51af67fcd92f8514bf8c5a1ea8331aadd2bca171fb85f971c27ec17eaf7c31514 0012-ASoC-qcom-sm8250-Add-tdm-support.patch " diff --git a/device/testing/linux-xiaomi-pipa/config-xiaomi-pipa.aarch64 b/device/testing/linux-xiaomi-pipa/config-xiaomi-pipa.aarch64 index fd5ac9c0e..1cc0ff1cb 100644 --- a/device/testing/linux-xiaomi-pipa/config-xiaomi-pipa.aarch64 +++ b/device/testing/linux-xiaomi-pipa/config-xiaomi-pipa.aarch64 @@ -1,20 +1,19 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 6.19.10 Kernel Configuration +# Linux/arm64 6.19.11 Kernel Configuration # -CONFIG_CC_VERSION_TEXT="Alpine clang version 21.1.2" +CONFIG_CC_VERSION_TEXT="Alpine clang version 22.1.3" CONFIG_GCC_VERSION=0 CONFIG_CC_IS_CLANG=y -CONFIG_CLANG_VERSION=210102 +CONFIG_CLANG_VERSION=220103 CONFIG_AS_IS_LLVM=y -CONFIG_AS_VERSION=210102 +CONFIG_AS_VERSION=220103 CONFIG_LD_VERSION=0 CONFIG_LD_IS_LLD=y -CONFIG_LLD_VERSION=210102 -CONFIG_RUSTC_VERSION=109101 +CONFIG_LLD_VERSION=220103 +CONFIG_RUSTC_VERSION=109401 CONFIG_RUST_IS_AVAILABLE=y -CONFIG_RUSTC_LLVM_VERSION=210102 -CONFIG_CC_CAN_LINK=y +CONFIG_RUSTC_LLVM_VERSION=220101 CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y CONFIG_TOOLS_SUPPORT_RELR=y