linux-postmarketos-mediatek-mt81: new aport

Part-of: https://gitlab.postmarketos.org/postmarketOS/pmaports/-/merge_requests/6552
2025-05-25 14:08:32 -04:00 · 2025-05-25 14:08:32 -04:00 · 6923fa56e5
commit 6923fa56e5
parent 88963a9c4f
21 changed files with 10804 additions and 0 deletions
--- a/device/community/linux-postmarketos-mediatek-mt81/APKBUILD
+++ b/device/community/linux-postmarketos-mediatek-mt81/APKBUILD
@ -0,0 +1,116 @@
+# Maintainer: WeirdTreeThing <bradyn127@protonmail.com>
+pkgname=linux-postmarketos-mediatek-mt81
+pkgver=6.12.36
+pkgrel=0
+pkgdesc="Mainline kernel for mediatek mt8183/mt8192/mt8195/mt8186"
+arch="aarch64"
+_flavor="${pkgname#linux-}"
+url="https://kernel.org"
+license="GPL-2.0-only"
+options="!strip !check !tracedeps
+	pmb:cross-native
+	pmb:kconfigcheck-community
+	"
+makedepends="
+	bison
+	devicepkg-dev
+	findutils
+	flex
+	postmarketos-installkernel
+	openssl-dev
+	perl
+	rsync
+	gzip
+	xz
+	gmp-dev
+	mpc1-dev
+	mpfr-dev
+	lz4
+	zstd
+"
+replaces="linux-postmarketos-mtk-mt8183 linux-postmarketos-mediatek-mt8183 linux-postmarketos-mediatek-mt81xx"
+
+_carch="arm64"
+
+# Source
+_config="config-$_flavor.$CARCH"
+case $pkgver in
+	*.*.*)	_kernver=${pkgver%.0};;
+	*.*)	_kernver=$pkgver;;
+esac
+
+source="
+	https://cdn.kernel.org/pub/linux/kernel/v${_kernver%%.*}.x/linux-$_kernver.tar.xz
+	arm64-dts-mt8183-Add-kukui-jacuzzi-cerise-board.patch
+	arm64-dts-mediatek-Add-dts-for-hayato-rev5-sku0.patch
+	mt8183-fix-bluetooth.patch
+	mt8183-kukui-add-it6505-and-enable-dpi.patch
+	mt8183-kukui-jacuzzi-fix-display-resume.patch
+	mt8183-kukui-jacuzzi-hack-dpms-resume.patch
+	mt8183-kukui-jacuzzi-fennel14-rt1015p-sound.patch
+	wifi-rtw88-Fix-the-random-error-beacon-valid-message.patch
+	HACK-MTK-Disable-AFBC-support.patch
+	platform-chrome-cros_ec_typec-Purge-blocking-switch-devlinks.patch
+	drm-Display-Add-Type-C-switch-helpers.patch
+	drm-bridge-anx7625-Register-Type-C-mode-switches.patch
+	drm-bridge-anx7625-Check-for-Type-C-during-panel-registration.patch
+	STOPSHIP-arm64-dts-mediatek-asurada-Add-DP.patch
+	STOPSHIP-arm64-dts-mediatek-asurada-Enable-HDMI-audio.patch
+	mt8186-enable-dpi.patch
+	mt8186-add-extcon-to-dp-bridge.patch
+	mt8195-adsp.patch
+	mt8195-dvfsrc.patch
+	config-$_flavor.aarch64
+"
+builddir="$srcdir/linux-$_kernver"
+
+prepare() {
+	default_prepare
+	cp "$srcdir/config-$_flavor.$CARCH" .config
+}
+
+build() {
+	unset LDFLAGS
+	make ARCH="$_carch" \
+		KBUILD_BUILD_VERSION="$((pkgrel + 1 ))-$_flavor"
+}
+
+package() {
+	mkdir -p "$pkgdir"/boot
+
+	make zinstall modules_install dtbs_install \
+		ARCH="$_carch" \
+		INSTALL_PATH="$pkgdir"/boot \
+		INSTALL_MOD_PATH="$pkgdir" \
+		INSTALL_MOD_STRIP=1 \
+		INSTALL_DTBS_PATH="$pkgdir"/boot/dtbs
+	rm -f "$pkgdir"/lib/modules/*/build "$pkgdir"/lib/modules/*/source
+
+	install -D "$builddir"/include/config/kernel.release \
+		"$pkgdir"/usr/share/kernel/$_flavor/kernel.release
+}
+
+
+sha512sums="
+17f540e00c4f5e457e64211c29d6b8c8dc7c9e7a523be070cced0423ef68a3c068a956561de069f4a7719009506908696219c524c27953c4b02fadfa37db808e  linux-6.12.36.tar.xz
+a95ce4a71d249ef401ca04cf8faf85b9022114d35fef5a0ce18929f734a0ac80ed0332648cc9768625f3c26b3720679e1a20bf8ac564087bd4c64f49cd96cc45  arm64-dts-mt8183-Add-kukui-jacuzzi-cerise-board.patch
+bf39ed6646a869a7a99dc7f0ccc7bbaca0c50776e87848cb1a9e55bef317a73c08549a9acb8cce5c394ab3bf90667e4d1cf8a3671bb9de15d2a470d5e8be0261  arm64-dts-mediatek-Add-dts-for-hayato-rev5-sku0.patch
+d74da1231181835bec82015da1b3f5b08a1fe9c3c35dd712e285891094d94d9427ceac75d32f74be3a635e17d93ad82b37adf97db8176efc91aed17535023fc2  mt8183-fix-bluetooth.patch
+19fdf640c34a0c04ba6aca85e93650f8696fe16d2fd2dba2a79ed504c5e2813868f5dfd91f9b3ee6951eede2b2b1e295c7a0c0f5b462996316b4576973c82ddd  mt8183-kukui-add-it6505-and-enable-dpi.patch
+519b6468bca78d0e315c826592ae40dddca9daeba7c2b451a20ca996494cca45721833b9138fefbb543f53e0b9257c78ec4fec54de2a160aa8df730daf3ac996  mt8183-kukui-jacuzzi-fix-display-resume.patch
+e9a128a8ddd98c6c8957ba45186afa2ea8ebeac83d4f2db3ff9ee8a5dd8027af90868c334a7b456bfe7dce793517f27ad63efa220bc933e3407f6362da6d7b2a  mt8183-kukui-jacuzzi-hack-dpms-resume.patch
+9b8707de42635734031495da055c5860addeb656051540f1a14404b10aa8b501168d8b0e274b37bce989db3bc050e9beef722189556f6d782b92cc907731488d  mt8183-kukui-jacuzzi-fennel14-rt1015p-sound.patch
+21a927be9b660603e233c531969fc1f0376e508f2246fe9ff73c7c86dff12b1af394a0ee83698d06fcba0b1dd6ab1fd8c79b4bc7ec97729bb9d3e0acfcf633b8  wifi-rtw88-Fix-the-random-error-beacon-valid-message.patch
+ace10a0dca57917f382f21c421a2677f0a0d1a4efeeece54eaea24326098461c2b531f903d7fad81bf4f89f2ba4a58de801296af05ab0707d1b96b0e142ee1c9  HACK-MTK-Disable-AFBC-support.patch
+703faf3cc6e73bac514c6903c2bdc304c7cc6348c144bcca287a2e354535ed7ea97628b2bc26e06f8cc98c32cf4ae42f7bbb6bc1ca2592d3a954512d92efedce  platform-chrome-cros_ec_typec-Purge-blocking-switch-devlinks.patch
+d733766fa0fc49e4f29f76a8cd8f518fdf1bbd6655fd7bad63406ca8ed560518b72e8c8ee0a7ea6ea5af1b99df73f00972e9cf86e5dda6082b47c72744ce232c  drm-Display-Add-Type-C-switch-helpers.patch
+cc8f4cae5c8d69b4f67a2e60acbd772e7c315db182366d49417b255dc40f4a0ad416a4be7147721ce347de32340c073814869262acc950481297ef5575e66dc4  drm-bridge-anx7625-Register-Type-C-mode-switches.patch
+539668541846798f49eb2661246a1ecdb475f70cf781cd1529b676a136a49f67bb5a0d27547756acf29bafea25c3c1caf3fb0a35d7591ea2b60aa4c334695336  drm-bridge-anx7625-Check-for-Type-C-during-panel-registration.patch
+0e6be6a08b88cdcb1cbf4010388131252d24618053815848cafbd81e1b4b6d82d9ae99760b154f65e0bb08a197554957fa9f83e625977e34da2ec83f00a4654e  STOPSHIP-arm64-dts-mediatek-asurada-Add-DP.patch
+982e5d7eb6460544f5014bd303ca6972d06ada6c71b3633e972e6b5cd4ab10dfb9eb40e4f80971fe6325a437661521503f7dc4aef3010cfada013fc399fd36ad  STOPSHIP-arm64-dts-mediatek-asurada-Enable-HDMI-audio.patch
+e4eaff9d3ec1a56ae2503dd353ad57bf072219e68c26ba8b894feb90d6ccb01bd131cdde8d238451258679aca1203a9ebdd888f01ee2a118d46f981ff4bcf54c  mt8186-enable-dpi.patch
+8854ac2bcd728261d47c2756d2e9081d0f399766fb305a460cd38d394d5620aef06dc46a4e986a21e34ecd1527c4f73d3e1c86e47ce855437716be94604d6d24  mt8186-add-extcon-to-dp-bridge.patch
+7582a86506ec1ff0a08ae52d249fa465f436439b01b592fe01f7aaa2fbdb3b2ae989473cd5cd9d39e6e9dac60d847063fa66ef36b808be695aa62b512d722d2b  mt8195-adsp.patch
+c61890785079aa67a4b92a30955cc7b2b1e1f8460255f2391b3d11f76c0e9568fe7dc9710e542392d42bf0a4426e1d47d7287621166e0cc9aa0333382ebd2cd2  mt8195-dvfsrc.patch
+9990a6ba76a641cd9724e8b4369c1792a9650fbdf44142ca69dec83eff0bf56cac200fa3a0ec6e47380949e29988518dcf73c1aa96572a0387367ba3d19eccec  config-postmarketos-mediatek-mt81.aarch64
+"
--- a/device/community/linux-postmarketos-mediatek-mt81/HACK-MTK-Disable-AFBC-support.patch
+++ b/device/community/linux-postmarketos-mediatek-mt81/HACK-MTK-Disable-AFBC-support.patch
@ -0,0 +1,44 @@
+From 8f40003af37e1567e53fdfcb6446ab4b90755bc0 Mon Sep 17 00:00:00 2001
+From: Sjoerd Simons <sjoerd@collabora.com>
+Date: Tue, 4 Mar 2025 21:03:25 +0100
+Subject: [PATCH] HACK: MTK:  Disable AFBC support
+
+Starting with Mesa 25 AFBC will get more eagerly used. Unfortunately it
+seems both primary and overlay planes on Genio 700 and Genio 1200 are
+broken in this regard. On 1200 it results in odd corrupted frames, while
+on 700 it results in vblank timeouts (for primary planes)
+
+Add a HACK to disable AFBC for now until this can be further diagnosed
+---
+ drivers/gpu/drm/mediatek/mtk_plane.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/mediatek/mtk_plane.c b/drivers/gpu/drm/mediatek/mtk_plane.c
+index 655106bbb76d3..02162780adf4f 100644
+--- a/drivers/gpu/drm/mediatek/mtk_plane.c
+++ b/drivers/gpu/drm/mediatek/mtk_plane.c
+@@ -21,9 +21,11 @@
+ 
+ static const u64 modifiers[] = {
+ 	DRM_FORMAT_MOD_LINEAR,
+	/* HACK disable AFBC support for now
+ 	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 |
+ 				AFBC_FORMAT_MOD_SPLIT |
+ 				AFBC_FORMAT_MOD_SPARSE),
+				*/
+ 	DRM_FORMAT_MOD_INVALID,
+ };
+ 
+@@ -74,6 +76,9 @@ static bool mtk_plane_format_mod_supported(struct drm_plane *plane,
+ 	if (modifier == DRM_FORMAT_MOD_LINEAR)
+ 		return true;
+ 
+	/* HACK: Disable AFBC support for all planes */
+	return false;
+
+ 	if (modifier != DRM_FORMAT_MOD_ARM_AFBC(
+ 				AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 |
+ 				AFBC_FORMAT_MOD_SPLIT |
+-- 
+GitLab
+
--- a/device/community/linux-postmarketos-mediatek-mt81/STOPSHIP-arm64-dts-mediatek-asurada-Add-DP.patch
+++ b/device/community/linux-postmarketos-mediatek-mt81/STOPSHIP-arm64-dts-mediatek-asurada-Add-DP.patch
@ -0,0 +1,217 @@
+From 47790019dab8ddffc7998fe2d35b6f70226ea533 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?=
+ <nfraprado@collabora.com>
+Date: Tue, 22 Mar 2022 18:43:27 -0400
+Subject: [PATCH] STOPSHIP: arm64: dts: mediatek: asurada: Add DP
+
+---
+ .../boot/dts/mediatek/mt8192-asurada.dtsi     | 158 ++++++++++++++++++
+ 1 file changed, 158 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+index dd0d07fbe61a8..5778f3e4de39e 100644
+--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+@@ -276,6 +276,20 @@ sound: sound {
+ 	};
+ };
+ 
+&dpi0 {
+	status = "okay";
+
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&dpi_default_pins>;
+	pinctrl-1 = <&dpi_sleep_pins>;
+
+	port {
+		dpi_out: endpoint {
+			remote-endpoint = <&anx7625_dp_in>;
+		};
+	};
+};
+
+ &dsi0 {
+ 	status = "okay";
+ };
+@@ -407,6 +421,65 @@ &i2c7 {
+ 	clock-frequency = <400000>;
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&i2c7_pins>;
+
+	anx_bridge_dp: anx7625@58 {
+		compatible = "analogix,anx7625";
+		reg = <0x58>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&anx7625_dp_pins>;
+		enable-gpios = <&pio 8 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&pio 9 GPIO_ACTIVE_HIGH>;
+		interrupt-parent = <&pio>;
+		interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
+		vdd10-supply = <&pp1000_dpbrdg>;
+		vdd18-supply = <&pp1800_dpbrdg>;
+		vdd33-supply = <&pp3300_dpbrdg>;
+		analogix,lane0-swing = /bits/ 8 <0x14 0x54 0x64 0x74
+						 0x29 0x7b 0x77 0x5b
+						 0x7f 0x7f 0x3f 0x3c
+						 0x20 0x60 0x3c 0x25
+						 0x60 0x2c 0x40 0x60>;
+		analogix,lane1-swing = /bits/ 8 <0x14 0x54 0x64 0x74
+						 0x29 0x7b 0x77 0x5b
+						 0x7f 0x7f 0x3f 0x3c
+						 0x20 0x60 0x3c 0x25
+						 0x60 0x2c 0x40 0x60>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				anx7625_dp_in: endpoint {
+					bus-type = <7>;
+					remote-endpoint = <&dpi_out>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				anx_typec0: endpoint@0 {
+					reg = <0>;
+					data-lanes = <2 3>;
+					mode-switch;
+					remote-endpoint = <&typec_port0>;
+				};
+
+				anx_typec1: endpoint@1 {
+					reg = <1>;
+					data-lanes = <0 1>;
+					mode-switch;
+					remote-endpoint = <&typec_port1>;
+				};
+			};
+		};
+	};
+ };
+ 
+ &mfg0 {
+@@ -759,6 +832,20 @@ &pio {
+ 			  "AUD_DAT_MISO0",
+ 			  "AUD_DAT_MISO1";
+ 
+	anx7625_dp_pins: anx7625-dp-default-pins {
+		pins-out {
+			pinmux = <PINMUX_GPIO8__FUNC_GPIO8>,
+				 <PINMUX_GPIO9__FUNC_GPIO9>;
+			output-low;
+		};
+
+		pins-in {
+			pinmux = <PINMUX_GPIO7__FUNC_GPIO7>;
+			input-enable;
+			bias-pull-up;
+		};
+	};
+
+ 	anx7625_pins: anx7625-default-pins {
+ 		pins-out {
+ 			pinmux = <PINMUX_GPIO41__FUNC_GPIO41>,
+@@ -947,6 +1034,51 @@ pins-ec-ap-int-odl {
+ 		};
+ 	};
+ 
+	dpi_sleep_pins: dpi-sleep-pins {
+		pins {
+			pinmux = <PINMUX_GPIO96__FUNC_GPIO96>,
+				<PINMUX_GPIO97__FUNC_GPIO97>,
+				<PINMUX_GPIO98__FUNC_GPIO98>,
+				<PINMUX_GPIO99__FUNC_GPIO99>,
+				<PINMUX_GPIO100__FUNC_GPIO100>,
+				<PINMUX_GPIO101__FUNC_GPIO101>,
+				<PINMUX_GPIO102__FUNC_GPIO102>,
+				<PINMUX_GPIO103__FUNC_GPIO103>,
+				<PINMUX_GPIO104__FUNC_GPIO104>,
+				<PINMUX_GPIO105__FUNC_GPIO105>,
+				<PINMUX_GPIO106__FUNC_GPIO106>,
+				<PINMUX_GPIO110__FUNC_GPIO110>,
+				<PINMUX_GPIO113__FUNC_GPIO113>,
+				<PINMUX_GPIO111__FUNC_GPIO111>,
+				<PINMUX_GPIO109__FUNC_GPIO109>,
+				<PINMUX_GPIO112__FUNC_GPIO112>;
+			drive-strength = <14>;
+			output-low;
+		};
+	};
+
+	dpi_default_pins: dpi-default-pins {
+		pins {
+			pinmux = <PINMUX_GPIO96__FUNC_DPI_D0>,
+				<PINMUX_GPIO97__FUNC_DPI_D1>,
+				<PINMUX_GPIO98__FUNC_DPI_D2>,
+				<PINMUX_GPIO99__FUNC_DPI_D3>,
+				<PINMUX_GPIO100__FUNC_DPI_D4>,
+				<PINMUX_GPIO101__FUNC_DPI_D5>,
+				<PINMUX_GPIO102__FUNC_DPI_D6>,
+				<PINMUX_GPIO103__FUNC_DPI_D7>,
+				<PINMUX_GPIO104__FUNC_DPI_D8>,
+				<PINMUX_GPIO105__FUNC_DPI_D9>,
+				<PINMUX_GPIO106__FUNC_DPI_D10>,
+				<PINMUX_GPIO110__FUNC_DPI_D11>,
+				<PINMUX_GPIO113__FUNC_DPI_HSYNC>,
+				<PINMUX_GPIO111__FUNC_DPI_VSYNC>,
+				<PINMUX_GPIO109__FUNC_DPI_DE>,
+				<PINMUX_GPIO112__FUNC_DPI_CK>;
+			drive-strength = <14>;
+		};
+	};
+
+ 	i2c0_pins: i2c0-default-pins {
+ 		pins-bus {
+ 			pinmux = <PINMUX_GPIO204__FUNC_SCL0>,
+@@ -1376,6 +1508,19 @@ usb_c0: connector@0 {
+ 				power-role = "dual";
+ 				data-role = "host";
+ 				try-power-role = "source";
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@1 {
+						reg = <1>;
+
+						typec_port0: endpoint {
+							remote-endpoint = <&anx_typec0>;
+						};
+					};
+				};
+ 			};
+ 
+ 			usb_c1: connector@1 {
+@@ -1385,6 +1530,19 @@ usb_c1: connector@1 {
+ 				power-role = "dual";
+ 				data-role = "host";
+ 				try-power-role = "source";
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@1 {
+						reg = <1>;
+
+						typec_port1: endpoint {
+							remote-endpoint = <&anx_typec1>;
+						};
+					};
+				};
+ 			};
+ 		};
+ 	};
+-- 
+GitLab
+
--- a/device/community/linux-postmarketos-mediatek-mt81/STOPSHIP-arm64-dts-mediatek-asurada-Enable-HDMI-audio.patch
+++ b/device/community/linux-postmarketos-mediatek-mt81/STOPSHIP-arm64-dts-mediatek-asurada-Enable-HDMI-audio.patch
@ -0,0 +1,33 @@
+From a28c1bf6a6b7883b516978d3282d01bc9abd4798 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?=
+ <nfraprado@collabora.com>
+Date: Mon, 25 Apr 2022 17:30:38 -0400
+Subject: [PATCH] STOPSHIP: arm64: dts: mediatek: asurada: Enable HDMI audio
+
+---
+ arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+index 5778f3e4de39e..4d08fdf81793b 100644
+--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+@@ -221,6 +221,7 @@ rt1015p: audio-codec {
+ 
+ 	sound: sound {
+ 		mediatek,platform = <&afe>;
+		mediatek,hdmi-codec = <&anx_bridge_dp>;
+ 		pinctrl-names = "aud_clk_mosi_off",
+ 				"aud_clk_mosi_on",
+ 				"aud_dat_mosi_off",
+@@ -444,6 +445,7 @@ anx_bridge_dp: anx7625@58 {
+ 						 0x7f 0x7f 0x3f 0x3c
+ 						 0x20 0x60 0x3c 0x25
+ 						 0x60 0x2c 0x40 0x60>;
+		analogix,audio-enable;
+ 
+ 		ports {
+ 			#address-cells = <1>;
+-- 
+GitLab
+
--- a/device/community/linux-postmarketos-mediatek-mt81/arm64-dts-mediatek-Add-dts-for-hayato-rev5-sku0.patch
+++ b/device/community/linux-postmarketos-mediatek-mt81/arm64-dts-mediatek-Add-dts-for-hayato-rev5-sku0.patch
@ -0,0 +1,179 @@
+From c80f01c470f12f7365c356617cbfbc81215c3734 Mon Sep 17 00:00:00 2001
+From: WeirdTreeThing <bradyn127@protonmail.com>
+Date: Fri, 28 Jun 2024 13:29:07 -0400
+Subject: [PATCH 1/2] arm64: dts: mediatek: Add dts for hayato rev5 sku0
+
+---
+ arch/arm64/boot/dts/mediatek/Makefile         |   1 +
+ .../mt8192-asurada-hayato-r5-sku0.dts         | 147 ++++++++++++++++++
+ 2 files changed, 148 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r5-sku0.dts
+
+diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
+index 37b4ca3a87c9..fe7950b68f5a 100644
+--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
+@@ -65,6 +65,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacruel-sku262148.dtb
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-evb.dtb
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r1.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r5-sku0.dtb
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r5-sku2.dtb
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r0.dtb
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r4.dtb
+diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r5-sku0.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r5-sku0.dts
+new file mode 100644
+index 000000000000..a1376631019d
+--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r5-sku0.dts
+@@ -0,0 +1,147 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2020 Google LLC
+ */
+/dts-v1/;
+#include "mt8192-asurada.dtsi"
+
+/ {
+	model = "Google Hayato rev5 sku0";
+	compatible = "google,hayato-rev5-sku0", "google,hayato-rev5",
+                     "google,hayato-sku0", "google,hayato", "mediatek,mt8192";
+};
+
+&keyboard_controller {
+	function-row-physmap = <
+		MATRIX_KEY(0x00, 0x02, 0)	/* T1 */
+		MATRIX_KEY(0x03, 0x02, 0)	/* T2 */
+		MATRIX_KEY(0x02, 0x02, 0)	/* T3 */
+		MATRIX_KEY(0x01, 0x02, 0)	/* T4 */
+		MATRIX_KEY(0x03, 0x04, 0)	/* T5 */
+		MATRIX_KEY(0x02, 0x04, 0)	/* T6 */
+		MATRIX_KEY(0x01, 0x04, 0)	/* T7 */
+		MATRIX_KEY(0x02, 0x09, 0)	/* T8 */
+		MATRIX_KEY(0x01, 0x09, 0)	/* T9 */
+		MATRIX_KEY(0x00, 0x04, 0)	/* T10 */
+	>;
+	linux,keymap = <
+		MATRIX_KEY(0x00, 0x02, KEY_BACK)
+		MATRIX_KEY(0x03, 0x02, KEY_FORWARD)
+		MATRIX_KEY(0x02, 0x02, KEY_REFRESH)
+		MATRIX_KEY(0x01, 0x02, KEY_FULL_SCREEN)
+		MATRIX_KEY(0x03, 0x04, KEY_SCALE)
+		MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)
+		MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)
+		MATRIX_KEY(0x02, 0x09, KEY_MUTE)
+		MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)
+		MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
+
+		CROS_STD_MAIN_KEYMAP
+	>;
+};
+
+&pio {
+	bt_pins: bt-pins {
+		pins-bt-kill {
+			pinmux = <PINMUX_GPIO144__FUNC_GPIO144>;
+			output-low;
+		};
+
+		pins-bt-wake {
+			pinmux = <PINMUX_GPIO22__FUNC_GPIO22>;
+			bias-pull-up;
+		};
+
+		pins-ap-wake-bt {
+			pinmux = <PINMUX_GPIO168__FUNC_GPIO168>;
+			output-low;
+		};
+	};
+
+	uart1_pins: uart1-pins {
+		pins-rx {
+			pinmux = <PINMUX_GPIO94__FUNC_URXD1>;
+			input-enable;
+			bias-pull-up;
+		};
+
+		pins-tx {
+			pinmux = <PINMUX_GPIO95__FUNC_UTXD1>;
+		};
+
+		pins-cts {
+			pinmux = <PINMUX_GPIO166__FUNC_UCTS1>;
+			input-enable;
+		};
+
+		pins-rts {
+			pinmux = <PINMUX_GPIO167__FUNC_URTS1>;
+		};
+	};
+
+	uart1_pins_sleep: uart1-sleep-pins {
+		pins-rx {
+			pinmux = <PINMUX_GPIO94__FUNC_GPIO94>;
+			input-enable;
+			bias-pull-up;
+		};
+
+		pins-tx {
+			pinmux = <PINMUX_GPIO95__FUNC_UTXD1>;
+		};
+
+		pins-cts {
+			pinmux = <PINMUX_GPIO166__FUNC_UCTS1>;
+			input-enable;
+		};
+
+		pins-rts {
+			pinmux = <PINMUX_GPIO167__FUNC_URTS1>;
+		};
+	};
+};
+
+&rt5682 {
+	compatible = "realtek,rt5682i";
+	realtek,btndet-delay = <16>;
+	VBAT-supply = <&pp3300_ldo_z>;
+};
+
+&sound {
+	compatible = "mediatek,mt8192_mt6359_rt1015p_rt5682";
+
+	speaker-codecs {
+		sound-dai = <&rt1015p>;
+	};
+
+	headset-codec {
+		sound-dai = <&rt5682 0>;
+	};
+};
+
+&touchscreen {
+	compatible = "hid-over-i2c";
+	post-power-on-delay-ms = <10>;
+	hid-descr-addr = <0x0001>;
+	vdd-supply = <&pp3300_u>;
+};
+
+&uart1 {
+	status = "okay";
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&uart1_pins>;
+	pinctrl-1 = <&uart1_pins_sleep>;
+	/delete-property/ interrupts;
+	interrupts-extended = <&gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>,
+			      <&pio 94 IRQ_TYPE_EDGE_FALLING>;
+
+	bluetooth {
+		compatible = "realtek,rtl8822cs-bt";
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_pins>;
+
+		enable-gpios = <&pio 144 GPIO_ACTIVE_HIGH>;
+		device-wake-gpios = <&pio 168 GPIO_ACTIVE_HIGH>;
+		host-wake-gpios = <&pio 22 GPIO_ACTIVE_LOW>;
+	};
+};
+-- 
+2.45.2
+
--- a/device/community/linux-postmarketos-mediatek-mt81/arm64-dts-mt8183-Add-kukui-jacuzzi-cerise-board.patch
+++ b/device/community/linux-postmarketos-mediatek-mt81/arm64-dts-mt8183-Add-kukui-jacuzzi-cerise-board.patch
@ -0,0 +1,181 @@
+diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
+index ebef3873e..93523a22d 100644
+--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
+@@ -22,6 +22,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana-rev7.dtb
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-burnet.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-cerise.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-cerise-rev3.dtb
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-cozmo.dtb
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-damu.dtb
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku1.dtb
+@@ -32,6 +34,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel14-sku2.dtb
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-juniper-sku16.dtb
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kappa.dtb
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kenzo.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-stern.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-stern-rev3.dtb
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-makomo-sku0.dtb
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-makomo-sku1.dtb
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-pico.dtb
+diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cerise-rev3.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cerise-rev3.dts
+new file mode 100644
+index 000000000..2776d9356
+--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cerise-rev3.dts
+@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi-cerise.dtsi"
+
+/ {
+	model = "Google cerise board";
+	compatible = "google,cerise-rev3-sku0", "google,cerise", "mediatek,mt8183";
+};
+
+&mt6358codec {
+	mediatek,dmic-mode = <1>; /* one-wire */
+};
+
+&touchscreen {
+	status = "disabled";
+};
+
+&qca_wifi {
+	qcom,ath10k-calibration-variant = "GO_CERISE";
+};
+diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cerise.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cerise.dts
+new file mode 100644
+index 000000000..418b5024d
+--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cerise.dts
+@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi-cerise.dtsi"
+
+/ {
+	model = "Google cerise board";
+	compatible = "google,cerise-sku0", "google,cerise", "mediatek,mt8183";
+};
+
+&mt6358codec {
+	mediatek,dmic-mode = <1>; /* one-wire */
+};
+
+&touchscreen {
+	status = "disabled";
+};
+
+&qca_wifi {
+	qcom,ath10k-calibration-variant = "GO_CERISE";
+};
+diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cerise.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cerise.dtsi
+new file mode 100644
+index 000000000..ec1561ac3
+--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cerise.dtsi
+@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi.dtsi"
+
+&mmc1_pins_uhs {
+	pins_clk {
+		drive-strength = <MTK_DRIVE_6mA>;
+	};
+};
+diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-stern-rev3.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-stern-rev3.dts
+new file mode 100644
+index 000000000..05303c4ed
+--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-stern-rev3.dts
+@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi-cerise.dtsi"
+
+/ {
+	model = "Google stern board";
+	compatible = "google,cerise-rev3-sku1", "google,cerise", "mediatek,mt8183";
+};
+
+&mt6358codec {
+	mediatek,dmic-mode = <0>; /* two-wire */
+};
+
+&touchscreen {
+	status = "okay";
+
+	compatible = "hid-over-i2c";
+	reg = <0x10>;
+	interrupt-parent = <&pio>;
+	interrupts = <155 IRQ_TYPE_LEVEL_LOW>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&touchscreen_pins>;
+
+	post-power-on-delay-ms = <10>;
+	hid-descr-addr = <0x0001>;
+};
+
+&qca_wifi {
+	qcom,ath10k-calibration-variant = "GO_STERN";
+};
+diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-stern.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-stern.dts
+new file mode 100644
+index 000000000..5be767bc8
+--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-stern.dts
+@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi-cerise.dtsi"
+
+/ {
+	model = "Google stern board";
+	compatible = "google,cerise-sku1", "google,cerise", "mediatek,mt8183";
+};
+
+&mt6358codec {
+	mediatek,dmic-mode = <0>; /* two-wire */
+};
+
+&touchscreen {
+	status = "okay";
+
+	compatible = "hid-over-i2c";
+	reg = <0x10>;
+	interrupt-parent = <&pio>;
+	interrupts = <155 IRQ_TYPE_LEVEL_LOW>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&touchscreen_pins>;
+
+	post-power-on-delay-ms = <10>;
+	hid-descr-addr = <0x0001>;
+};
+
+&qca_wifi {
+	qcom,ath10k-calibration-variant = "GO_STERN";
+};
--- a/device/community/linux-postmarketos-mediatek-mt81/config-postmarketos-mediatek-mt81.aarch64
+++ b/device/community/linux-postmarketos-mediatek-mt81/config-postmarketos-mediatek-mt81.aarch64
--- a/device/community/linux-postmarketos-mediatek-mt81/drm-Display-Add-Type-C-switch-helpers.patch
+++ b/device/community/linux-postmarketos-mediatek-mt81/drm-Display-Add-Type-C-switch-helpers.patch
@ -0,0 +1,207 @@
+diff --git a/drivers/gpu/drm/display/Kconfig b/drivers/gpu/drm/display/Kconfig
+index 3b824e01c..4d082a2e7 100644
+--- a/drivers/gpu/drm/display/Kconfig
+++ b/drivers/gpu/drm/display/Kconfig
+@@ -64,6 +64,14 @@ config DRM_DISPLAY_DP_TUNNEL_STATE_DEBUG
+ 
+ 	  If in doubt, say "N".
+ 
+config DRM_DISPLAY_DP_TYPEC_HELPER
+	def_bool y
+	depends on DRM_DISPLAY_HELPER
+	depends on DRM_DISPLAY_HELPER=TYPEC || TYPEC=y
+	help
+	  Choose this option to enable helpers for registering USB Type-C
+	  switches when USB Type-C DisplayPort Alternate mode is used.
+
+ config DRM_DISPLAY_HDCP_HELPER
+ 	bool
+ 	help
+diff --git a/drivers/gpu/drm/display/Makefile b/drivers/gpu/drm/display/Makefile
+index fbb9d2b8a..df56f8870 100644
+--- a/drivers/gpu/drm/display/Makefile
+++ b/drivers/gpu/drm/display/Makefile
+@@ -12,6 +12,8 @@ drm_display_helper-$(CONFIG_DRM_DISPLAY_DP_HELPER) += \
+ 	drm_dsc_helper.o
+ drm_display_helper-$(CONFIG_DRM_DISPLAY_DP_TUNNEL) += \
+ 	drm_dp_tunnel.o
+drm_display_helper-$(CONFIG_DRM_DISPLAY_DP_TYPEC_HELPER) += \
+   drm_dp_typec_helper.o
+ drm_display_helper-$(CONFIG_DRM_DISPLAY_HDCP_HELPER) += drm_hdcp_helper.o
+ drm_display_helper-$(CONFIG_DRM_DISPLAY_HDMI_HELPER) += \
+ 	drm_hdmi_helper.o \
+diff --git a/drivers/gpu/drm/display/drm_dp_typec_helper.c b/drivers/gpu/drm/display/drm_dp_typec_helper.c
+new file mode 100644
+index 000000000..48c1bbf57
+--- /dev/null
+++ b/drivers/gpu/drm/display/drm_dp_typec_helper.c
+@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <linux/usb/typec_mux.h>
+#include <drm/display/drm_dp_helper.h>
+
+static int drm_dp_register_mode_switch(struct device *dev,
+				       struct fwnode_handle *fwnode,
+				       struct drm_dp_typec_switch_desc *switch_desc,
+				       void *data, typec_mux_set_fn_t mux_set)
+{
+	struct drm_dp_typec_port_data *port_data;
+	struct typec_mux_desc mux_desc = {};
+	char name[32];
+	u32 port_num;
+	int ret;
+
+	ret = fwnode_property_read_u32(fwnode, "reg", &port_num);
+	if (ret) {
+		dev_err(dev, "Failed to read reg property: %d\n", ret);
+		return ret;
+	}
+
+	port_data = &switch_desc->typec_ports[port_num];
+	port_data->data = data;
+	port_data->port_num = port_num;
+	port_data->fwnode = fwnode;
+	mux_desc.fwnode = fwnode;
+	mux_desc.drvdata = port_data;
+	snprintf(name, sizeof(name), "%s-%u", dev_name(dev), port_num);
+	mux_desc.name = name;
+	mux_desc.set = mux_set;
+
+	port_data->typec_mux = typec_mux_register(dev, &mux_desc);
+	ret = PTR_ERR_OR_ZERO(port_data->typec_mux);
+	if (ret)
+		dev_err(dev, "Mode switch register for port %d failed: %d\n",
+			port_num, ret);
+
+	return ret;
+}
+
+/**
+ * drm_dp_register_typec_switches() - register Type-C switches
+ * @dev: Device that registers Type-C switches
+ * @port: Device node for the switch
+ * @switch_desc: A Type-C switch descriptor
+ * @data: Private data for the switches
+ * @mux_set: Callback function for typec_mux_set
+ *
+ * This function registers USB Type-C switches for DP bridges that can switch
+ * the output signal between their output pins. This function uses devm_kcalloc
+ * to allocate memory, so it is expected to only call this in the driver probe
+ * functions.
+ *
+ * Currently only mode switches are implemented, and the function assumes the
+ * given @port device node has endpoints with "mode-switch" property.
+ * The port number is determined by the "reg" property of the endpoint.
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+int drm_dp_register_typec_switches(struct device *dev, struct fwnode_handle *port,
+				   struct drm_dp_typec_switch_desc *switch_desc,
+				   void *data, typec_mux_set_fn_t mux_set)
+{
+	struct fwnode_handle *sw;
+	int ret;
+
+	switch_desc->num_typec_switches = typec_mode_switch_node_count(port);
+	if (!switch_desc->num_typec_switches) {
+		dev_dbg(dev, "No Type-C switches node found\n");
+		return 0;
+	}
+
+	switch_desc->typec_ports = devm_kcalloc(dev, switch_desc->num_typec_switches,
+						sizeof(*switch_desc->typec_ports),
+						GFP_KERNEL);
+	if (!switch_desc->typec_ports)
+		return -ENOMEM;
+
+	/* Register switches for each connector. */
+	for_each_typec_mode_switch_node(port, sw) {
+		ret = drm_dp_register_mode_switch(dev, sw, switch_desc, data, mux_set);
+		if (ret)
+			goto err_unregister_typec_switches;
+	}
+
+	return 0;
+
+err_unregister_typec_switches:
+	fwnode_handle_put(sw);
+	drm_dp_unregister_typec_switches(switch_desc);
+	return ret;
+}
+EXPORT_SYMBOL(drm_dp_register_typec_switches);
+
+/**
+ * drm_dp_unregister_typec_switches() - unregister Type-C switches
+ * @switch_desc: A Type-C switch descriptor
+ */
+void drm_dp_unregister_typec_switches(struct drm_dp_typec_switch_desc *switch_desc)
+{
+	unsigned int i;
+
+	for (i = 0; i < switch_desc->num_typec_switches; i++)
+		typec_mux_unregister(switch_desc->typec_ports[i].typec_mux);
+}
+EXPORT_SYMBOL(drm_dp_unregister_typec_switches);
+diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
+index 279624833..9417c034c 100644
+--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
+@@ -25,6 +25,7 @@
+ 
+ #include <linux/delay.h>
+ #include <linux/i2c.h>
+#include <linux/usb/typec_mux.h>
+ 
+ #include <drm/display/drm_dp.h>
+ #include <drm/drm_connector.h>
+@@ -874,4 +875,49 @@ int drm_dp_max_dprx_data_rate(int max_link_rate, int max_lanes);
+ 
+ ssize_t drm_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, struct dp_sdp *sdp);
+ 
+struct drm_dp_typec_port_data {
+	struct typec_mux_dev *typec_mux;
+	struct fwnode_handle *fwnode;
+	void *data;
+	int port_num;
+};
+
+struct drm_dp_typec_switch_desc {
+	struct drm_dp_typec_port_data *typec_ports;
+	int num_typec_switches;
+};
+
+#define for_each_typec_mode_switch_node(port, sw)	\
+	fwnode_for_each_child_node((port), (sw))	\
+		for_each_if(fwnode_property_present((sw), "mode-switch"))
+
+static inline unsigned int typec_mode_switch_node_count(struct fwnode_handle *port)
+{
+	struct fwnode_handle *sw;
+	unsigned int count = 0;
+
+	for_each_typec_mode_switch_node(port, sw)
+		count++;
+
+	return count;
+}
+
+#ifdef CONFIG_DRM_DISPLAY_DP_TYPEC_HELPER
+void drm_dp_unregister_typec_switches(struct drm_dp_typec_switch_desc *switch_desc);
+int drm_dp_register_typec_switches(struct device *dev, struct fwnode_handle *port,
+				   struct drm_dp_typec_switch_desc *switch_desc,
+				   void *data, typec_mux_set_fn_t mux_set);
+#else
+static inline void drm_dp_unregister_typec_switches(struct drm_dp_typec_switch_desc *switch_desc)
+{
+}
+static inline int drm_dp_register_typec_switches(
+		struct device *dev, struct fwnode_handle *port,
+		struct drm_dp_typec_switch_desc *switch_desc, void *data,
+		typec_mux_set_fn_t mux_set)
+{
+	return -EOPNOTSUPP;
+}
+#endif
+
+ #endif /* _DRM_DP_HELPER_H_ */
--- a/device/community/linux-postmarketos-mediatek-mt81/drm-bridge-anx7625-Check-for-Type-C-during-panel-registration.patch
+++ b/device/community/linux-postmarketos-mediatek-mt81/drm-bridge-anx7625-Check-for-Type-C-during-panel-registration.patch
@ -0,0 +1,22 @@
+diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c
+index c30425b4e..a037055bc 100644
+--- a/drivers/gpu/drm/bridge/analogix/anx7625.c
+++ b/drivers/gpu/drm/bridge/analogix/anx7625.c
+@@ -1715,6 +1715,17 @@ static int anx7625_parse_dt_panel(struct device *dev,
+ 				  struct anx7625_platform_data *pdata)
+ {
+ 	struct device_node *np = dev->of_node;
+	struct device_node *port_node;
+	unsigned int count;
+
+	/*
+	 * Don't bother finding a panel if a Type-C `mode-switch` property is
+	 * present in one of the endpoints in the output port.
+	 */
+	port_node = of_graph_get_port_by_id(np, 1);
+	count = typec_mode_switch_node_count(&port_node->fwnode);
+	if (count)
+		return 0;
+ 
+ 	pdata->panel_bridge = devm_drm_of_get_bridge(dev, np, 1, 0);
+ 	if (IS_ERR(pdata->panel_bridge)) {
--- a/device/community/linux-postmarketos-mediatek-mt81/drm-bridge-anx7625-Register-Type-C-mode-switches.patch
+++ b/device/community/linux-postmarketos-mediatek-mt81/drm-bridge-anx7625-Register-Type-C-mode-switches.patch
@ -0,0 +1,241 @@
+diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c
+index fcc04f258..92b1f5cfa 100644
+--- a/drivers/gpu/drm/bridge/analogix/anx7625.c
+++ b/drivers/gpu/drm/bridge/analogix/anx7625.c
+@@ -15,6 +15,8 @@
+ #include <linux/regulator/consumer.h>
+ #include <linux/slab.h>
+ #include <linux/types.h>
+#include <linux/usb/typec_dp.h>
+#include <linux/usb/typec_mux.h>
+ #include <linux/workqueue.h>
+ 
+ #include <linux/of_graph.h>
+@@ -2640,6 +2642,154 @@ static int anx7625_link_bridge(struct drm_dp_aux *aux)
+ 	return ret;
+ }
+ 
+static void anx7625_set_crosspoint_switch(struct anx7625_data *ctx,
+					  enum typec_orientation orientation)
+{
+	if (orientation == TYPEC_ORIENTATION_NORMAL) {
+		anx7625_reg_write(ctx, ctx->i2c.tcpc_client, TCPC_SWITCH_0,
+				  SW_SEL1_SSRX_RX1 | SW_SEL1_DPTX0_RX2);
+		anx7625_reg_write(ctx, ctx->i2c.tcpc_client, TCPC_SWITCH_1,
+				  SW_SEL2_SSTX_TX1 | SW_SEL2_DPTX1_TX2);
+	} else if (orientation == TYPEC_ORIENTATION_REVERSE) {
+		anx7625_reg_write(ctx, ctx->i2c.tcpc_client, TCPC_SWITCH_0,
+				  SW_SEL1_SSRX_RX2 | SW_SEL1_DPTX0_RX1);
+		anx7625_reg_write(ctx, ctx->i2c.tcpc_client, TCPC_SWITCH_1,
+				  SW_SEL2_SSTX_TX2 | SW_SEL2_DPTX1_TX1);
+	}
+}
+
+static void anx7625_typec_two_ports_update(struct anx7625_data *ctx)
+{
+	unsigned int i;
+
+	/* Check if both ports available and do nothing to retain the current one */
+	if (ctx->port_data[0].dp_connected && ctx->port_data[1].dp_connected)
+		return;
+
+	for (i = 0; i < 2; i++) {
+		if (ctx->port_data[i].dp_connected)
+			anx7625_set_crosspoint_switch(ctx,
+						      ctx->port_data[i].orientation);
+	}
+}
+
+static int anx7625_typec_mux_set(struct typec_mux_dev *mux,
+				 struct typec_mux_state *state)
+{
+	struct drm_dp_typec_port_data *port = typec_mux_get_drvdata(mux);
+	struct anx7625_data *ctx = port->data;
+	struct device *dev = ctx->dev;
+	struct drm_dp_typec_switch_desc switch_desc = ctx->switch_desc;
+	bool new_dp_connected, old_dp_connected;
+
+	if (switch_desc.num_typec_switches == 1)
+		return 0;
+
+	/*
+	 * The completion is called in anx7625_register_typec_switches
+	 * even on errors, so it's safe to wait for completion without timeout.
+	 */
+	wait_for_completion(&ctx->mux_register);
+
+	/* Abort when the switches are unregistered. */
+	if (!ctx->port_data)
+		return -EINVAL;
+
+	old_dp_connected = ctx->port_data[0].dp_connected ||
+			   ctx->port_data[1].dp_connected;
+
+	ctx->port_data[port->port_num].dp_connected =
+		state->alt &&
+		state->alt->svid == USB_TYPEC_DP_SID &&
+		state->alt->mode == USB_TYPEC_DP_MODE;
+
+	dev_dbg(dev, "mux_set dp_connected: c0=%d, c1=%d\n",
+		ctx->port_data[0].dp_connected, ctx->port_data[1].dp_connected);
+
+	new_dp_connected = ctx->port_data[0].dp_connected ||
+			   ctx->port_data[1].dp_connected;
+
+	/* DP on, power on first */
+	if (!old_dp_connected && new_dp_connected)
+		pm_runtime_get_sync(dev);
+
+	anx7625_typec_two_ports_update(ctx);
+
+	/* DP off, power off last */
+	if (old_dp_connected && !new_dp_connected)
+		pm_runtime_put_sync(dev);
+
+	return 0;
+}
+
+static void anx7625_unregister_typec_switches(struct anx7625_data *ctx)
+{
+	drm_dp_unregister_typec_switches(&ctx->switch_desc);
+	ctx->port_data = NULL;
+}
+
+static int anx7625_register_typec_switches(struct device *dev, struct anx7625_data *ctx)
+{
+	struct device_node *port_node = of_graph_get_port_by_id(dev->of_node, 1);
+	struct drm_dp_typec_switch_desc *switch_desc = &ctx->switch_desc;
+	int ret;
+	u32 dp_lanes[4];
+	unsigned int i, num_lanes;
+
+	/*
+	 * Currently, only mode switch is implemented.
+	 * TODO: Implement Type-C orientation switch for anx7625.
+	 */
+	ret = drm_dp_register_typec_switches(dev, &port_node->fwnode,
+					     &ctx->switch_desc, ctx,
+					     anx7625_typec_mux_set);
+	if (ret)
+		return ret;
+
+	ctx->port_data = devm_kcalloc(dev, switch_desc->num_typec_switches,
+				      sizeof(*ctx->port_data),
+				      GFP_KERNEL);
+	if (!ctx->port_data) {
+		ret = -ENOMEM;
+		goto unregister_mux;
+	}
+
+	for (i = 0; i < switch_desc->num_typec_switches; i++) {
+		struct drm_dp_typec_port_data *port = &switch_desc->typec_ports[i];
+		struct fwnode_handle *fwnode = port->fwnode;
+
+		ret = fwnode_property_count_u32(fwnode, "data-lanes");
+		if (ret < 0) {
+			dev_err(dev,
+				"Error on getting data lanes count from %pfwP: %d\n",
+				fwnode, ret);
+			goto unregister_mux;
+		}
+		num_lanes = ret;
+
+		ret = fwnode_property_read_u32_array(fwnode, "data-lanes",
+						     dp_lanes, num_lanes);
+		if (ret) {
+			dev_err(dev,
+				"Failed to read the data-lanes variable: %d\n",
+				ret);
+			goto unregister_mux;
+		}
+
+		ctx->port_data[i].orientation = dp_lanes[0] < 2 ?
+			TYPEC_ORIENTATION_REVERSE : TYPEC_ORIENTATION_NORMAL;
+		ctx->port_data[i].dp_connected = false;
+	}
+	complete_all(&ctx->mux_register);
+
+	return 0;
+
+unregister_mux:
+	anx7625_unregister_typec_switches(ctx);
+	complete_all(&ctx->mux_register);
+	return ret;
+}
+
+ static int anx7625_i2c_probe(struct i2c_client *client)
+ {
+ 	struct anx7625_data *platform;
+@@ -2678,6 +2828,7 @@ static int anx7625_i2c_probe(struct i2c_client *client)
+ 	mutex_init(&platform->lock);
+ 	mutex_init(&platform->hdcp_wq_lock);
+ 	mutex_init(&platform->aux_lock);
+	init_completion(&platform->mux_register);
+ 
+ 	INIT_DELAYED_WORK(&platform->hdcp_work, hdcp_check_work_func);
+ 	platform->hdcp_workqueue = create_workqueue("hdcp workqueue");
+@@ -2774,6 +2925,10 @@ static int anx7625_i2c_probe(struct i2c_client *client)
+ 	if (platform->pdata.intp_irq)
+ 		queue_work(platform->workqueue, &platform->work);
+ 
+	ret = anx7625_register_typec_switches(dev, platform);
+	if (ret && ret != -ENODEV)
+		dev_warn(dev, "Didn't register Type-C switches, err: %d\n", ret);
+
+ 	if (platform->pdata.audio_en)
+ 		anx7625_register_audio(dev, platform);
+ 
+@@ -2798,6 +2953,8 @@ static void anx7625_i2c_remove(struct i2c_client *client)
+ 
+ 	drm_bridge_remove(&platform->bridge);
+ 
+	anx7625_unregister_typec_switches(platform);
+
+ 	if (platform->pdata.intp_irq)
+ 		destroy_workqueue(platform->workqueue);
+ 
+diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.h b/drivers/gpu/drm/bridge/analogix/anx7625.h
+index 439ed2b24..5cfcef6f3 100644
+--- a/drivers/gpu/drm/bridge/analogix/anx7625.h
+++ b/drivers/gpu/drm/bridge/analogix/anx7625.h
+@@ -55,6 +55,18 @@
+ #define HPD_STATUS_CHANGE 0x80
+ #define HPD_STATUS 0x80
+ 
+#define TCPC_SWITCH_0 0xB4 
+#define SW_SEL1_DPTX0_RX2 BIT(0)
+#define SW_SEL1_DPTX0_RX1 BIT(1)
+#define SW_SEL1_SSRX_RX2 BIT(4)
+#define SW_SEL1_SSRX_RX1 BIT(5)
+
+#define TCPC_SWITCH_1 0xB5
+#define SW_SEL2_DPTX1_TX2 BIT(0)
+#define SW_SEL2_DPTX1_TX1 BIT(1)
+#define SW_SEL2_SSTX_TX2 BIT(4)
+#define SW_SEL2_SSTX_TX1 BIT(5)
+
+ /******** END of I2C Address 0x58 ********/
+ 
+ /***************************************************************/
+@@ -447,6 +459,11 @@ struct anx7625_i2c_client {
+ 	struct i2c_client *tcpc_client;
+ };
+ 
+struct anx7625_typec_port_data {
+	enum typec_orientation orientation;
+	bool dp_connected;
+};
+
+ struct anx7625_data {
+ 	struct anx7625_platform_data pdata;
+ 	struct platform_device *audio_pdev;
+@@ -480,6 +497,9 @@ struct anx7625_data {
+ 	struct mipi_dsi_device *dsi;
+ 	struct drm_dp_aux aux;
+ 	struct device_link *link;
+	struct completion mux_register;
+	struct drm_dp_typec_switch_desc switch_desc;
+	struct anx7625_typec_port_data *port_data;
+ };
+ 
+ #endif  /* __ANX7625_H__ */
--- a/device/community/linux-postmarketos-mediatek-mt81/mt8183-fix-bluetooth.patch
+++ b/device/community/linux-postmarketos-mediatek-mt81/mt8183-fix-bluetooth.patch
@ -0,0 +1,93 @@
+this reverts drivers/tty/serial/8250/8250_mtk.c back to the v5.17 version
+as otherwise it breaks bluetooth on mt8183 kukui devices
+
+diff --git a/drivers/tty/serial/8250/8250_mtk.c b/drivers/tty/serial/8250/8250_mtk.c
+index 54051ec7b499..fb65dc601b23 100644
+--- a/drivers/tty/serial/8250/8250_mtk.c
+++ b/drivers/tty/serial/8250/8250_mtk.c
+@@ -37,7 +37,6 @@
+ #define MTK_UART_IER_RTSI	0x40	/* Enable RTS Modem status interrupt */
+ #define MTK_UART_IER_CTSI	0x80	/* Enable CTS Modem status interrupt */
+ 
+-#define MTK_UART_EFR		38	/* I/O: Extended Features Register */
+ #define MTK_UART_EFR_EN		0x10	/* Enable enhancement feature */
+ #define MTK_UART_EFR_RTS	0x40	/* Enable hardware rx flow control */
+ #define MTK_UART_EFR_CTS	0x80	/* Enable hardware tx flow control */
+@@ -54,9 +53,6 @@
+ #define MTK_UART_TX_TRIGGER	1
+ #define MTK_UART_RX_TRIGGER	MTK_UART_RX_SIZE
+ 
+-#define MTK_UART_XON1		40	/* I/O: Xon character 1 */
+-#define MTK_UART_XOFF1		42	/* I/O: Xoff character 1 */
+-
+ #ifdef CONFIG_SERIAL_8250_DMA
+ enum dma_rx_status {
+ 	DMA_RX_START = 0,
+@@ -173,7 +169,7 @@ static void mtk8250_dma_enable(struct uart_8250_port *up)
+ 		   MTK_UART_DMA_EN_RX | MTK_UART_DMA_EN_TX);
+ 
+ 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
+-	serial_out(up, MTK_UART_EFR, UART_EFR_ECB);
+	serial_out(up, UART_EFR, UART_EFR_ECB);
+ 	serial_out(up, UART_LCR, lcr);
+ 
+ 	if (dmaengine_slave_config(dma->rxchan, &dma->rxconf) != 0)
+@@ -236,7 +232,7 @@ static void mtk8250_set_flow_ctrl(struct uart_8250_port *up, int mode)
+ 	int lcr = serial_in(up, UART_LCR);
+ 
+ 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
+-	serial_out(up, MTK_UART_EFR, UART_EFR_ECB);
+	serial_out(up, UART_EFR, UART_EFR_ECB);
+ 	serial_out(up, UART_LCR, lcr);
+ 	lcr = serial_in(up, UART_LCR);
+ 
+@@ -245,7 +241,7 @@ static void mtk8250_set_flow_ctrl(struct uart_8250_port *up, int mode)
+ 		serial_out(up, MTK_UART_ESCAPE_DAT, MTK_UART_ESCAPE_CHAR);
+ 		serial_out(up, MTK_UART_ESCAPE_EN, 0x00);
+ 		serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
+-		serial_out(up, MTK_UART_EFR, serial_in(up, MTK_UART_EFR) &
+		serial_out(up, UART_EFR, serial_in(up, UART_EFR) &
+ 			(~(MTK_UART_EFR_HW_FC | MTK_UART_EFR_SW_FC_MASK)));
+ 		serial_out(up, UART_LCR, lcr);
+ 		mtk8250_disable_intrs(up, MTK_UART_IER_XOFFI |
+@@ -259,8 +255,8 @@ static void mtk8250_set_flow_ctrl(struct uart_8250_port *up, int mode)
+ 		serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
+ 
+ 		/*enable hw flow control*/
+-		serial_out(up, MTK_UART_EFR, MTK_UART_EFR_HW_FC |
+-			(serial_in(up, MTK_UART_EFR) &
+		serial_out(up, UART_EFR, MTK_UART_EFR_HW_FC |
+			(serial_in(up, UART_EFR) &
+ 			(~(MTK_UART_EFR_HW_FC | MTK_UART_EFR_SW_FC_MASK))));
+ 
+ 		serial_out(up, UART_LCR, lcr);
+@@ -274,12 +270,12 @@ static void mtk8250_set_flow_ctrl(struct uart_8250_port *up, int mode)
+ 		serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
+ 
+ 		/*enable sw flow control */
+-		serial_out(up, MTK_UART_EFR, MTK_UART_EFR_XON1_XOFF1 |
+-			(serial_in(up, MTK_UART_EFR) &
+		serial_out(up, UART_EFR, MTK_UART_EFR_XON1_XOFF1 |
+			(serial_in(up, UART_EFR) &
+ 			(~(MTK_UART_EFR_HW_FC | MTK_UART_EFR_SW_FC_MASK))));
+ 
+-		serial_out(up, MTK_UART_XON1, START_CHAR(port->state->port.tty));
+-		serial_out(up, MTK_UART_XOFF1, STOP_CHAR(port->state->port.tty));
+		serial_out(up, UART_XON1, START_CHAR(port->state->port.tty));
+		serial_out(up, UART_XOFF1, STOP_CHAR(port->state->port.tty));
+ 		serial_out(up, UART_LCR, lcr);
+ 		mtk8250_disable_intrs(up, MTK_UART_IER_CTSI|MTK_UART_IER_RTSI);
+ 		mtk8250_enable_intrs(up, MTK_UART_IER_XOFFI);
+@@ -293,10 +289,10 @@ static void
+ mtk8250_set_termios(struct uart_port *port, struct ktermios *termios,
+ 			struct ktermios *old)
+ {
+-	static const unsigned short fraction_L_mapping[] = {
+	unsigned short fraction_L_mapping[] = {
+ 		0, 1, 0x5, 0x15, 0x55, 0x57, 0x57, 0x77, 0x7F, 0xFF, 0xFF
+ 	};
+-	static const unsigned short fraction_M_mapping[] = {
+	unsigned short fraction_M_mapping[] = {
+ 		0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 3
+ 	};
+ 	struct uart_8250_port *up = up_to_u8250p(port);
--- a/device/community/linux-postmarketos-mediatek-mt81/mt8183-kukui-add-it6505-and-enable-dpi.patch
+++ b/device/community/linux-postmarketos-mediatek-mt81/mt8183-kukui-add-it6505-and-enable-dpi.patch
@ -0,0 +1,139 @@
+from: https://chromium.googlesource.com/chromiumos/third_party/kernel/+/55500342cfdb02f5550481df77c2d3a541b73e93%5E%21/#F0
+
+diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
+index 8155658..50f84ae 100644
+--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
+
+@@ -259,6 +259,18 @@ &cpu7 {
+ 	proc-supply = <&mt6358_vproc11_reg>;
+ };
+ 
+&dpi0 {
+	pinctrl-names = "sleep", "default";
+	pinctrl-0 = <&dpi_pin_default>;
+	pinctrl-1 = <&dpi_pin_func>;
+	status = "okay";
+	port {
+		dpi_out: endpoint {
+			remote-endpoint = <&it6505_in>;
+		};
+	};
+};
+
+ &dsi0 {
+ 	status = "okay";
+ 	#address-cells = <1>;
+@@ -321,6 +333,27 @@ &i2c3 {
+ 	clock-frequency = <100000>;
+ 	#address-cells = <1>;
+ 	#size-cells = <0>;
+
+	it6505dptx: it6505dptx@5c {
+		compatible = "ite,it6505";
+		status = "okay";
+		interrupt-parent = <&pio>;
+		interrupts = <152 IRQ_TYPE_LEVEL_LOW 152 0>;
+		reg = <0x5c>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&it6505_pins>;
+		ovdd-supply = <&mt6358_vsim2_reg>;
+		pwr18-supply = <&it6505_pp18_reg>;
+		reset-gpios = <&pio 179 GPIO_ACTIVE_HIGH>;
+		hpd-gpios = <&pio 9 0>;
+		extcon = <&usbc_extcon>;
+		no-laneswap;
+		port {
+			it6505_in: endpoint {
+				remote-endpoint = <&dpi_out>;
+			};
+		};
+	};
+ };
+ 
+ &i2c5 {
+@@ -515,6 +548,51 @@ pins_cmd_dat {
+ 		};
+ 	};
+ 
+	dpi_pin_default: dpi_pin_default {
+		pins_cmd_dat {
+			pinmux = <PINMUX_GPIO13__FUNC_GPIO13>,
+				<PINMUX_GPIO14__FUNC_GPIO14>,
+				<PINMUX_GPIO15__FUNC_GPIO15>,
+				<PINMUX_GPIO16__FUNC_GPIO16>,
+				<PINMUX_GPIO17__FUNC_GPIO17>,
+				<PINMUX_GPIO18__FUNC_GPIO18>,
+				<PINMUX_GPIO19__FUNC_GPIO19>,
+				<PINMUX_GPIO20__FUNC_GPIO20>,
+				<PINMUX_GPIO21__FUNC_GPIO21>,
+				<PINMUX_GPIO22__FUNC_GPIO22>,
+				<PINMUX_GPIO23__FUNC_GPIO23>,
+				<PINMUX_GPIO24__FUNC_GPIO24>,
+				<PINMUX_GPIO25__FUNC_GPIO25>,
+				<PINMUX_GPIO26__FUNC_GPIO26>,
+				<PINMUX_GPIO27__FUNC_GPIO27>,
+				<PINMUX_GPIO28__FUNC_GPIO28>;
+				drive-strength = <MTK_DRIVE_6mA>;
+				output-low;
+		};
+	};
+
+	dpi_pin_func: dpi_pin_func {
+		pins_cmd_dat {
+			pinmux = <PINMUX_GPIO13__FUNC_DBPI_D0>,
+				<PINMUX_GPIO14__FUNC_DBPI_D1>,
+				<PINMUX_GPIO15__FUNC_DBPI_D2>,
+				<PINMUX_GPIO16__FUNC_DBPI_D3>,
+				<PINMUX_GPIO17__FUNC_DBPI_D4>,
+				<PINMUX_GPIO18__FUNC_DBPI_D5>,
+				<PINMUX_GPIO19__FUNC_DBPI_D6>,
+				<PINMUX_GPIO20__FUNC_DBPI_D7>,
+				<PINMUX_GPIO21__FUNC_DBPI_D8>,
+				<PINMUX_GPIO22__FUNC_DBPI_D9>,
+				<PINMUX_GPIO23__FUNC_DBPI_D10>,
+				<PINMUX_GPIO24__FUNC_DBPI_D11>,
+				<PINMUX_GPIO25__FUNC_DBPI_HSYNC>,
+				<PINMUX_GPIO26__FUNC_DBPI_VSYNC>,
+				<PINMUX_GPIO27__FUNC_DBPI_DE>,
+				<PINMUX_GPIO28__FUNC_DBPI_CK>;
+				drive-strength = <MTK_DRIVE_6mA>;
+		};
+	};
+
+ 	ec_ap_int_odl: ec-ap-int-odl {
+ 		pins1 {
+ 			pinmux = <PINMUX_GPIO151__FUNC_GPIO151>;
+@@ -586,6 +664,32 @@ pins-bus {
+ 		};
+ 	};
+ 
+	it6505_pins: it6505_pins {
+		pins_hpd {
+			pinmux = <PINMUX_GPIO9__FUNC_GPIO9>;
+			input-enable;
+			bias-pull-up;
+		};
+
+		pins_int {
+			pinmux = <PINMUX_GPIO152__FUNC_GPIO152>;
+			input-enable;
+			bias-pull-up;
+		};
+
+		pins_power_enable {
+			pinmux = <PINMUX_GPIO178__FUNC_GPIO178>;
+			output-low;
+			bias-pull-up;
+		};
+
+		pins_reset {
+			pinmux = <PINMUX_GPIO179__FUNC_GPIO179>;
+			output-low;
+			bias-pull-up;
+		};
+	};
+
+ 	mmc0_pins_default: mmc0-pins-default {
+ 		pins-cmd-dat {
+ 			pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
--- a/device/community/linux-postmarketos-mediatek-mt81/mt8183-kukui-jacuzzi-fennel14-rt1015p-sound.patch
+++ b/device/community/linux-postmarketos-mediatek-mt81/mt8183-kukui-jacuzzi-fennel14-rt1015p-sound.patch
@ -0,0 +1,13 @@
+removes a dapm sound route, that prevents loading the kernel module
+
+--- a/sound/soc/mediatek/mt8183/mt8183-da7219-max98357.c
+++ b/sound/soc/mediatek/mt8183/mt8183-da7219-max98357.c
+@@ -590,7 +590,7 @@
+ 
+ static const struct snd_soc_dapm_route mt8183_da7219_max98357_dapm_routes[] = {
+ 	{"Speakers", NULL, "Speaker"},
+-	{"I2S Playback", NULL, "TDM_OUT_PINCTRL"},
+//	{"I2S Playback", NULL, "TDM_OUT_PINCTRL"},
+ };
+ 
+ static struct snd_soc_card mt8183_da7219_max98357_card = {
--- a/device/community/linux-postmarketos-mediatek-mt81/mt8183-kukui-jacuzzi-fix-display-resume.patch
+++ b/device/community/linux-postmarketos-mediatek-mt81/mt8183-kukui-jacuzzi-fix-display-resume.patch
@ -0,0 +1,63 @@
+from: https://patchwork.kernel.org/project/linux-mediatek/patch/20210720100553.2340425-1-pihsun@chromium.org/
+      [v2] drm/bridge: anx7625: Use pm_runtime_force_{suspend, resume}
+
+diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c
+index 14d73fb1dd15..8325e8d0ee19 100644
+--- a/drivers/gpu/drm/bridge/analogix/anx7625.c
+++ b/drivers/gpu/drm/bridge/analogix/anx7625.c
+@@ -1349,6 +1349,8 @@ static void anx7625_bridge_detach(struct drm_bridge *bridge)
+ 		mipi_dsi_detach(ctx->dsi);
+ 		mipi_dsi_device_unregister(ctx->dsi);
+ 	}
+	if (ctx->link)
+		device_link_del(ctx->link);
+ }
+ 
+ static int anx7625_bridge_attach(struct drm_bridge *bridge,
+@@ -1373,17 +1375,33 @@ static int anx7625_bridge_attach(struct drm_bridge *bridge,
+ 		return err;
+ 	}
+ 
+	ctx->link = device_link_add(bridge->dev->dev, dev, DL_FLAG_STATELESS);
+	if (!ctx->link) {
+		DRM_DEV_ERROR(dev, "device link creation failed");
+		err = -EINVAL;
+		goto detach_dsi;
+	}
+
+ 	if (ctx->pdata.panel_bridge) {
+ 		err = drm_bridge_attach(bridge->encoder,
+ 					ctx->pdata.panel_bridge,
+ 					&ctx->bridge, flags);
+ 		if (err)
+-			return err;
+			goto remove_device_link;
+ 	}
+ 
+ 	ctx->bridge_attached = 1;
+ 
+ 	return 0;
+
+remove_device_link:
+	device_link_del(ctx->link);
+detach_dsi:
+	if (ctx->dsi) {
+		mipi_dsi_detach(ctx->dsi);
+		mipi_dsi_device_unregister(ctx->dsi);
+	}
+	return err;
+ }
+ 
+ static enum drm_mode_status
+diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.h b/drivers/gpu/drm/bridge/analogix/anx7625.h
+index edbbfe410a56..299e62df6238 100644
+--- a/drivers/gpu/drm/bridge/analogix/anx7625.h
+++ b/drivers/gpu/drm/bridge/analogix/anx7625.h
+@@ -473,6 +473,7 @@ struct anx7625_data {
+ 	struct drm_connector *connector;
+ 	struct mipi_dsi_device *dsi;
+ 	struct drm_dp_aux aux;
+	struct device_link *link;
+ };
+ 
+ #endif  /* __ANX7625_H__ */
--- a/device/community/linux-postmarketos-mediatek-mt81/mt8183-kukui-jacuzzi-hack-dpms-resume.patch
+++ b/device/community/linux-postmarketos-mediatek-mt81/mt8183-kukui-jacuzzi-hack-dpms-resume.patch
@ -0,0 +1,16 @@
+this is most probably not the proper solution, but it at least lets the display
+come back properly after a dpms suspend ...
+
+diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c
+index 31ecf5626f1d..6763b280dab4 100644
+--- a/drivers/gpu/drm/bridge/analogix/anx7625.c
+++ b/drivers/gpu/drm/bridge/analogix/anx7625.c
+@@ -1425,6 +1427,8 @@ static void anx7625_start_dp_work(struct anx7625_data *ctx)
+ 		return;
+ 
+ 	DRM_DEV_DEBUG_DRIVER(dev, "Secure OCM version=%02x\n", ret);
+
+	ctx->display_timing_valid = 1;
+ }
+ 
+ static int anx7625_read_hpd_status_p0(struct anx7625_data *ctx)
--- a/device/community/linux-postmarketos-mediatek-mt81/mt8186-add-extcon-to-dp-bridge.patch
+++ b/device/community/linux-postmarketos-mediatek-mt81/mt8186-add-extcon-to-dp-bridge.patch
@ -0,0 +1,39 @@
+from: https://patchwork.kernel.org/project/linux-mediatek/patch/20241212062046.22509-4-xiazhengqiao@huaqin.corp-partner.google.com/
+
+commit 79ef2aae9fde746217c82a3c659e73fa2583774d
+Author: Zhengqiao Xia <xiazhengqiao@huaqin.corp-partner.google.com>
+Date:   Thu Dec 12 14:20:45 2024 +0800
+
+    arm64: dts: mediatek: Add extcon node for DP bridge
+    
+    Add extcon node for DP bridge to make the display work properly.
+    
+    Signed-off-by: Zhengqiao Xia <xiazhengqiao@huaqin.corp-partner.google.com>
+    Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+    Link: https://lore.kernel.org/r/20241212062046.22509-4-xiazhengqiao@huaqin.corp-partner.google.com
+    Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+
+diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi b/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi
+index cfcc7909dfe6..e324e3fd347e 100644
+--- a/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi
+@@ -424,6 +424,7 @@ it6505dptx: dp-bridge@5c {
+ 		ovdd-supply = <&mt6366_vsim2_reg>;
+ 		pwr18-supply = <&pp1800_dpbrdg_dx>;
+ 		reset-gpios = <&pio 177 GPIO_ACTIVE_LOW>;
+		extcon = <&usbc_extcon>;
+ 
+ 		ports {
+ 			#address-cells = <1>;
+@@ -1656,6 +1657,11 @@ usb_c1: connector@1 {
+ 				try-power-role = "source";
+ 			};
+ 		};
+
+		usbc_extcon: extcon0 {
+			compatible = "google,extcon-usbc-cros-ec";
+			google,usb-port-id = <0>;
+		};
+ 	};
+ };
+ 
--- a/device/community/linux-postmarketos-mediatek-mt81/mt8186-enable-dpi.patch
+++ b/device/community/linux-postmarketos-mediatek-mt81/mt8186-enable-dpi.patch
@ -0,0 +1,14 @@
+diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi b/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi
+index cfcc7909dfe6..36f365816aec 100644
+--- a/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi
+@@ -353,8 +353,7 @@ &dpi {
+ 	pinctrl-names = "default", "sleep";
+ 	pinctrl-0 = <&dpi_pins_default>;
+ 	pinctrl-1 = <&dpi_pins_sleep>;
+-	/* TODO Re-enable after DP to Type-C port muxing can be described */
+-	status = "disabled";
+	status = "okay";
+ };
+ 
+ &dpi_out {
--- a/device/community/linux-postmarketos-mediatek-mt81/mt8195-adsp.patch
+++ b/device/community/linux-postmarketos-mediatek-mt81/mt8195-adsp.patch
@ -0,0 +1,36 @@
+From 16343aaad0b2886feb213e77d50c02d6e9917197 Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Date: Thu, 8 Sep 2022 11:44:30 +0200
+Subject: [PATCH] arm64: dts: mediatek: mt8195: Add ADSP power domains to ADSP
+ mailboxes
+
+Communication with the AudioDSP is impossible if it has no power.
+
+Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+---
+ arch/arm64/boot/dts/mediatek/mt8195.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+index 04e41b557d448..e2c771095dfa8 100644
+--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+@@ -969,6 +969,7 @@ adsp_mailbox0: mailbox@10816000 {
+ 			#mbox-cells = <0>;
+ 			reg = <0 0x10816000 0 0x1000>;
+ 			interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>;
+ 		};
+ 
+ 		adsp_mailbox1: mailbox@10817000 {
+@@ -976,6 +977,7 @@ adsp_mailbox1: mailbox@10817000 {
+ 			#mbox-cells = <0>;
+ 			reg = <0 0x10817000 0 0x1000>;
+ 			interrupts = <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>;
+ 		};
+ 
+ 		afe: mt8195-afe-pcm@10890000 {
+-- 
+GitLab
+
--- a/device/community/linux-postmarketos-mediatek-mt81/mt8195-dvfsrc.patch
+++ b/device/community/linux-postmarketos-mediatek-mt81/mt8195-dvfsrc.patch
@ -0,0 +1,62 @@
+From 26739d4dc862c6fc6b97d99b0d60a8dbc85a02c4 Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Date: Tue, 16 Apr 2024 16:29:11 +0200
+Subject: [PATCH] arm64: dts: mediatek: mt8195: Add DVFSRC and its subdevices
+
+Add a node for the Dynamic Voltage and Frequency Scaling Resource
+Collector (DVFSRC) and subnodes for the DVFSRC regulators, supplying
+power to CPU Cores and SCP, and External Memory Interface (EMI)
+interconnect.
+
+Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+---
+ arch/arm64/boot/dts/mediatek/mt8195.dtsi | 33 ++++++++++++++++++++++++
+ 1 file changed, 33 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+index cb9b6530910b3..c4d0d73374cd2 100644
+--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+@@ -863,6 +863,39 @@ apmixedsys: syscon@1000c000 {
+ 			#clock-cells = <1>;
+ 		};
+ 
+		system-controller@10012000 {
+			compatible = "mediatek,mt8195-dvfsrc";
+			reg = <0 0x10012000 0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			regulators {
+				compatible = "mediatek,mt8195-dvfsrc-regulator";
+				reg = <0>;
+
+				dvfsrc_vcore: dvfsrc-vcore {
+					regulator-name = "dvfsrc-vcore";
+					regulator-min-microvolt = <550000>;
+					regulator-max-microvolt = <750000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				dvfsrc_vscp: dvfsrc-vscp {
+					regulator-name = "dvfsrc-vcore";
+					regulator-min-microvolt = <550000>;
+					regulator-max-microvolt = <750000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+			};
+
+			emi_icc: interconnect {
+				compatible = "mediatek,mt8195-emi";
+				reg = <1>;
+			};
+		};
+
+ 		systimer: timer@10017000 {
+ 			compatible = "mediatek,mt8195-timer",
+ 				     "mediatek,mt6765-timer";
+-- 
+GitLab
+
--- a/device/community/linux-postmarketos-mediatek-mt81/platform-chrome-cros_ec_typec-Purge-blocking-switch-devlinks.patch
+++ b/device/community/linux-postmarketos-mediatek-mt81/platform-chrome-cros_ec_typec-Purge-blocking-switch-devlinks.patch
@ -0,0 +1,56 @@
+From d37fa510aab78b3605ca3e376053c156655d587c Mon Sep 17 00:00:00 2001
+From: Prashant Malani <pmalani@chromium.org>
+Date: Fri, 31 Mar 2023 17:11:37 +0800
+Subject: [PATCH] platform/chrome: cros_ec_typec: Purge blocking switch
+ devlinks
+
+When using OF graph, the fw_devlink code will create links between the
+individual port driver (cros-ec-typec here) and the parent device for
+a Type-C switch (like mode-switch). Since the mode-switch will in turn
+have the usb-c-connector (i.e the child of the port driver) as a
+supplier, fw_devlink will not be able to resolve the cyclic dependency
+correctly.
+
+As a result, the mode-switch driver probe() never runs, so mode-switches
+are never registered. Because of that, the port driver probe constantly
+fails with -EPROBE_DEFER, because the Type-C connector class requires all
+switch devices to be registered prior to port registration.
+
+To break this deadlock and allow the mode-switch registration to occur,
+purge all the usb-c-connector nodes' absent suppliers. This eliminates
+the connector as a supplier for a switch and allows it to be probed.
+
+Signed-off-by: Prashant Malani <pmalani@chromium.org>
+Signed-off-by: Pin-yen Lin <treapking@chromium.org>
+Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Tested-by: Chen-Yu Tsai <wenst@chromium.org>
+Acked-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
+---
+ drivers/platform/chrome/cros_ec_typec.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/drivers/platform/chrome/cros_ec_typec.c b/drivers/platform/chrome/cros_ec_typec.c
+index ae2f862969547..050e4277545b9 100644
+--- a/drivers/platform/chrome/cros_ec_typec.c
+++ b/drivers/platform/chrome/cros_ec_typec.c
+@@ -344,6 +344,16 @@ static int cros_typec_init_ports(struct cros_typec_data *typec)
+ 		return -EINVAL;
+ 	}
+ 
+	/*
+	 * OF graph may have set up some device links with switches,
+	 * since connectors have their own compatible. Purge these
+	 * to avoid a deadlock in switch probe (the switch mistakenly
+	 * assumes the connector is a supplier).
+	 */
+	if (dev_of_node(dev))
+		device_for_each_child_node(dev, fwnode)
+			fw_devlink_purge_absent_suppliers(fwnode);
+
+ 	/* DT uses "reg" to specify port number. */
+ 	port_prop = dev->of_node ? "reg" : "port-number";
+ 	device_for_each_child_node(dev, fwnode) {
+-- 
+GitLab
+
--- a/device/community/linux-postmarketos-mediatek-mt81/wifi-rtw88-Fix-the-random-error-beacon-valid-message.patch
+++ b/device/community/linux-postmarketos-mediatek-mt81/wifi-rtw88-Fix-the-random-error-beacon-valid-message.patch
@ -0,0 +1,76 @@
+From 6c04febdac5e03e2fded8386dc895c5326c82fa0 Mon Sep 17 00:00:00 2001
+From: Bitterblue Smith <rtl8821cerfe2@gmail.com>
+Date: Sat, 10 May 2025 16:12:34 +0300
+Subject: [PATCH] wifi: rtw88: Fix the random "error beacon valid" messages for
+ USB
+
+All the USB devices have a problem in AP mode: uploading the updated
+beacon to the chip's reserved page can randomly fail:
+
+[34996.474304] rtw88_8723du 1-2:1.2: error beacon valid
+[34996.474788] rtw88_8723du 1-2:1.2: failed to download drv rsvd page
+[34999.956369] rtw88_8723du 1-2:1.2: error beacon valid
+[34999.956846] rtw88_8723du 1-2:1.2: failed to download drv rsvd page
+[34999.956855] rtw88_8723du 1-2:1.2: failed to download beacon
+[35017.978296] rtw88_8723du 1-2:1.2: error beacon valid
+[35017.978805] rtw88_8723du 1-2:1.2: failed to download drv rsvd page
+[35017.978823] rtw88_8723du 1-2:1.2: failed to download beacon
+[35023.200395] rtw88_8723du 1-2:1.2: error beacon valid
+[35023.200869] rtw88_8723du 1-2:1.2: failed to download drv rsvd page
+[35023.200875] rtw88_8723du 1-2:1.2: failed to download beacon
+[35478.680547] rtw88_8723du 1-2:1.2: error beacon valid
+[35478.681023] rtw88_8723du 1-2:1.2: failed to download drv rsvd page
+
+Disable some beacon-related hardware functions before uploading the
+beacon and enable them again after.
+
+Tested with RTL8723DU, RTL8812BU, RTL8822CE.
+
+Signed-off-by: Bitterblue Smith <rtl8821cerfe2@gmail.com>
+---
+ drivers/net/wireless/realtek/rtw88/fw.c | 8 +++++++-
+ 1 file changed, 7 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/wireless/realtek/rtw88/fw.c b/drivers/net/wireless/realtek/rtw88/fw.c
+index b9b0114e253b..563b93f845fd 100644
+--- a/drivers/net/wireless/realtek/rtw88/fw.c
+++ b/drivers/net/wireless/realtek/rtw88/fw.c
+@@ -1443,7 +1443,7 @@ void rtw_add_rsvd_page_sta(struct rtw_dev *rtwdev,
+ int rtw_fw_write_data_rsvd_page(struct rtw_dev *rtwdev, u16 pg_addr,
+ 				u8 *buf, u32 size)
+ {
+-	u8 bckp[2];
+	u8 bckp[3];
+ 	u8 val;
+ 	u16 rsvd_pg_head;
+ 	u32 bcn_valid_addr;
+@@ -1455,6 +1455,8 @@ int rtw_fw_write_data_rsvd_page(struct rtw_dev *rtwdev, u16 pg_addr,
+ 	if (!size)
+ 		return -EINVAL;
+ 
+	bckp[2] = rtw_read8(rtwdev, REG_BCN_CTRL);
+
+ 	if (rtw_chip_wcpu_11n(rtwdev)) {
+ 		rtw_write32_set(rtwdev, REG_DWBCN0_CTRL, BIT_BCN_VALID);
+ 	} else {
+@@ -1468,6 +1470,9 @@ int rtw_fw_write_data_rsvd_page(struct rtw_dev *rtwdev, u16 pg_addr,
+ 	val |= BIT_ENSWBCN >> 8;
+ 	rtw_write8(rtwdev, REG_CR + 1, val);
+ 
+	rtw_write8(rtwdev, REG_BCN_CTRL,
+		   (bckp[2] & ~BIT_EN_BCN_FUNCTION) | BIT_DIS_TSF_UDT);
+
+ 	if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_PCIE) {
+ 		val = rtw_read8(rtwdev, REG_FWHW_TXQ_CTRL + 2);
+ 		bckp[1] = val;
+@@ -1498,6 +1503,7 @@ int rtw_fw_write_data_rsvd_page(struct rtw_dev *rtwdev, u16 pg_addr,
+ 	rsvd_pg_head = rtwdev->fifo.rsvd_boundary;
+ 	rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2,
+ 		    rsvd_pg_head | BIT_BCN_VALID_V1);
+	rtw_write8(rtwdev, REG_BCN_CTRL, bckp[2]);
+ 	if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_PCIE)
+ 		rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 2, bckp[1]);
+ 	rtw_write8(rtwdev, REG_CR + 1, bckp[0]);
+-- 
+2.49.0
+