From 3d4e9be606a3023dac0ac7ded8e53eaa8c0537a1 Mon Sep 17 00:00:00 2001
From: Joel Selvaraj <jo@jsfamily.in>
Date: Wed, 3 Feb 2021 19:54:45 +0000
Subject: [PATCH 02/12] power: supply: Add driver for Qualcomm PMIC fuel gauge

Ths driver supports the fuel gauge hardware available on PMICs such as PMI8994,
as well as gen 3 fuel gauge hardware available on PMI8998.

Co-developed-by: Caleb Connolly <caleb@connolly.tech>
Co-developed-by: Yassine Oudjana <y.oudjana@protonmail.com>
Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>

qcom_fg: expose PROP_STATUS to fix upower not detecting charging status properly

fg: adopt battery info API changes

power: qcom_fg: silence -EPROBE_DEFER error

Sometimes, the devm_power_supply_register function will return
ERR_PTR(-EPROBE_DEFER) to make the driver subsystem probe the fuel guage
later. This is not an error and do not report it as such.

Signed-off-by: Richard Acayan <mailingradian@gmail.com>

power/supply: qcom_fg: add present sysfs property

Present property is required for battery drivers from UPower>=1.90.0
onwards to work properly.

Signed-off-by: Alexander Martinz <amartinz@shiftphones.com>
Signed-off-by: map220v <map220v300@gmail.com>

power: qcom_fg: Add initial pm8150b support

power: qcom_fg: Fix memif address for pm8150b

power: qcom_fg: Fix wrong psy passed to power_supply_put_battery_info()

power: qcom_fg: Add support for temperature data on gen4 fg

arm64: dts: qcom: pm8150b: Add fuel gauge

qcom_fg: Fix compilation in 6.11

power: supply: qcom_fg: fix compile error

power: supply: Driver for Qualcomm SMB5

Signed-off-by: Teguh Sobirin <teguh@sobir.in>

arm64: dts: qcom: pm8150b: Add a charger

Signed-off-by: Teguh Sobirin <teguh@sobir.in>

power: supply: qcom_pm8150b_charger: adds charging control to pm8150b_charger
---
 arch/arm64/boot/dts/qcom/pm8150b.dtsi       |   40 +
 drivers/power/supply/Kconfig                |   17 +
 drivers/power/supply/Makefile               |    2 +
 drivers/power/supply/power_supply_sysfs.c   |    1 +
 drivers/power/supply/qcom_fg.c              | 1371 +++++++++++++++++++
 drivers/power/supply/qcom_pm8150b_charger.c |  964 +++++++++++++
 include/linux/power_supply.h                |    1 +
 7 files changed, 2390 insertions(+)
 create mode 100644 drivers/power/supply/qcom_fg.c
 create mode 100644 drivers/power/supply/qcom_pm8150b_charger.c

diff --git a/arch/arm64/boot/dts/qcom/pm8150b.dtsi b/arch/arm64/boot/dts/qcom/pm8150b.dtsi
index 3f7b0b6a1d10..4e9778c35402 100644
--- a/arch/arm64/boot/dts/qcom/pm8150b.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8150b.dtsi
@@ -107,6 +107,26 @@ pm8150b_temp: temp-alarm@2400 {
 			#thermal-sensor-cells = <0>;
 		};
 
+		pm8150b_charger: charger@1000 {
+			compatible = "qcom,pm8150b-charger";
+			reg = <0x1000>;
+
+			interrupts = <0x2 0x13 0x4 IRQ_TYPE_EDGE_BOTH>,
+				     <0x2 0x12 0x2 IRQ_TYPE_EDGE_BOTH>,
+				     <0x2 0x16 0x1 IRQ_TYPE_EDGE_RISING>,
+				     <0x2 0x13 0x7 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "usbin-plugin",
+					  "bat-ov",
+					  "wdog-bark",
+					  "usbin-icl-change";
+
+			io-channels = <&pm8150b_adc 7>,
+				      <&pm8150b_adc 8>;
+			io-channel-names = "usb_in_i_uv", "usb_in_v_div_16";
+
+			status = "disabled";
+		};
+
 		pm8150b_adc: adc@3100 {
 			compatible = "qcom,spmi-adc5";
 			reg = <0x3100>;
@@ -133,6 +153,18 @@ channel@6 {
 				label = "die_temp";
 			};
 
+			channel@7 {
+				reg = <ADC5_USB_IN_I>;
+				qcom,pre-scaling = <1 1>;
+				label = "usb_in_i_uv";
+			};
+
+			channel@8 {
+				reg = <ADC5_USB_IN_V_16>;
+				qcom,pre-scaling = <1 16>;
+				label = "usb_in_v_div_16";
+			};
+
 			channel@9 {
 				reg = <ADC5_CHG_TEMP>;
 				qcom,pre-scaling = <1 1>;
@@ -150,6 +182,14 @@ pm8150b_adc_tm: adc-tm@3500 {
 			status = "disabled";
 		};
 
+		pm8150b_fg: fuel-gauge@4000 {
+			compatible = "qcom,pm8150b-fg";
+			reg = <0x4000>;
+			interrupts = <0x2 0x40 0x3 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "soc-delta";
+			status = "disabled";
+		};
+
 		pm8150b_gpios: gpio@c000 {
 			compatible = "qcom,pm8150b-gpio", "qcom,spmi-gpio";
 			reg = <0xc000>;
diff --git a/drivers/power/supply/Kconfig b/drivers/power/supply/Kconfig
index 92f9f7aae92f..8fe78ef66fae 100644
--- a/drivers/power/supply/Kconfig
+++ b/drivers/power/supply/Kconfig
@@ -1122,6 +1122,15 @@ config CHARGER_QCOM_SMB2
 	  adds support for the SMB2 switch mode battery charger found
 	  in PMI8998 and related PMICs.
 
+config CHARGER_QCOM_SMB5
+	tristate "Qualcomm PMI8998 PMIC charger driver"
+	depends on MFD_SPMI_PMIC
+	depends on IIO
+	help
+	  Say Y here to enable the Qualcomm PMIC Charger driver. This
+	  adds support for the SMB5 switch mode battery charger found
+	  in PM8150B and related PMICs.
+
 config FUEL_GAUGE_MM8013
 	tristate "Mitsumi MM8013 fuel gauge driver"
 	depends on I2C
@@ -1132,4 +1141,12 @@ config FUEL_GAUGE_MM8013
 	  the state of charge, temperature, cycle count, actual and design
 	  capacity, etc.
 
+config BATTERY_QCOM_FG
+	tristate "Qualcomm PMIC fuel gauge driver"
+	depends on MFD_SPMI_PMIC
+	help
+	  Say Y here to enable the Qualcomm PMIC Fuel Gauge driver. This
+	  adds support for battery fuel gauging and state of charge of
+	  battery connected to the fuel gauge.
+
 endif # POWER_SUPPLY
diff --git a/drivers/power/supply/Makefile b/drivers/power/supply/Makefile
index 4b79d5abc49a..571233bdbd90 100644
--- a/drivers/power/supply/Makefile
+++ b/drivers/power/supply/Makefile
@@ -127,5 +127,7 @@ obj-$(CONFIG_BATTERY_SURFACE)	+= surface_battery.o
 obj-$(CONFIG_CHARGER_SURFACE)	+= surface_charger.o
 obj-$(CONFIG_BATTERY_UG3105)	+= ug3105_battery.o
 obj-$(CONFIG_CHARGER_QCOM_SMB2)	+= qcom_smbx.o
+obj-$(CONFIG_CHARGER_QCOM_SMB5)	+= qcom_pm8150b_charger.o
 obj-$(CONFIG_FUEL_GAUGE_MM8013)	+= mm8013.o
+obj-$(CONFIG_BATTERY_QCOM_FG)	+= qcom_fg.o
 obj-$(CONFIG_MACSMC_POWER)	+= macsmc-power.o
diff --git a/drivers/power/supply/power_supply_sysfs.c b/drivers/power/supply/power_supply_sysfs.c
index dd3a48d72d2b..5555b616acb1 100644
--- a/drivers/power/supply/power_supply_sysfs.c
+++ b/drivers/power/supply/power_supply_sysfs.c
@@ -225,6 +225,7 @@ static struct power_supply_attr power_supply_attrs[] __ro_after_init = {
 	POWER_SUPPLY_ATTR(MANUFACTURE_DAY),
 	POWER_SUPPLY_ATTR(INTERNAL_RESISTANCE),
 	POWER_SUPPLY_ATTR(STATE_OF_HEALTH),
+	POWER_SUPPLY_ATTR(CHARGING_ENABLED),
 	/* Properties of type `const char *' */
 	POWER_SUPPLY_ATTR(MODEL_NAME),
 	POWER_SUPPLY_ATTR(MANUFACTURER),
diff --git a/drivers/power/supply/qcom_fg.c b/drivers/power/supply/qcom_fg.c
new file mode 100644
index 000000000000..921ef52fcc60
--- /dev/null
+++ b/drivers/power/supply/qcom_fg.c
@@ -0,0 +1,1371 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (c) 2020, The Linux Foundation. All rights reserved. */
+
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/math64.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/power_supply.h>
+#include <linux/regmap.h>
+#include <linux/types.h>
+#include <linux/workqueue.h>
+
+/* SOC */
+#define BATT_MONOTONIC_SOC		0x009
+
+/* BATT */
+#define PARAM_ADDR_BATT_TEMP		0x150
+#define BATT_INFO_JEITA_COLD		0x162
+#define BATT_INFO_JEITA_COOL		0x163
+#define BATT_INFO_JEITA_WARM		0x164
+#define BATT_INFO_JEITA_HOT		0x165
+#define PARAM_ADDR_BATT_VOLTAGE		0x1a0
+#define PARAM_ADDR_BATT_CURRENT		0x1a2
+
+/* RRADC */
+#define ADC_RR_BATT_TEMP_LSB		0x288
+
+/* MEMIF */
+#define MEM_INTF_STS(chip)			(chip->ops->memif_base + 0x10)
+#define MEM_INTF_CFG(chip)			(chip->ops->memif_base + 0x50)
+#define MEM_INTF_CTL(chip)			(chip->ops->memif_base + 0x51)
+#define MEM_INTF_IMA_CFG(chip)			(chip->ops->memif_base + 0x52)
+#define MEM_INTF_IMA_EXP_STS(chip)		(chip->ops->memif_base + 0x55)
+#define MEM_INTF_IMA_HW_STS(chip)		(chip->ops->memif_base + 0x56)
+#define MEM_INTF_IMA_ERR_STS(chip)		(chip->ops->memif_base + 0x5f)
+#define MEM_INTF_IMA_BYTE_EN(chip)		(chip->ops->memif_base + 0x60)
+#define MEM_INTF_ADDR_LSB(chip)			(chip->ops->memif_base + 0x61)
+#define MEM_INTF_RD_DATA0(chip)			(chip->ops->memif_base + 0x67)
+#define MEM_INTF_WR_DATA0(chip)			(chip->ops->memif_base + 0x63)
+#define MEM_IF_DMA_STS(chip)			(chip->ops->memif_base + 0x70)
+#define MEM_IF_DMA_CTL(chip)			(chip->ops->memif_base + 0x71)
+
+/* SRAM addresses */
+#define TEMP_THRESHOLD			0x454
+#define BATT_TEMP			0x550
+#define BATT_VOLTAGE_CURRENT		0x5cc
+
+#define BATT_TEMP_LSB_MASK		GENMASK(7, 0)
+#define BATT_TEMP_MSB_MASK		GENMASK(2, 0)
+
+#define BATT_TEMP_JEITA_COLD		100
+#define BATT_TEMP_JEITA_COOL		50
+#define BATT_TEMP_JEITA_WARM		400
+#define BATT_TEMP_JEITA_HOT		450
+
+#define MEM_INTF_AVAIL			BIT(0)
+#define MEM_INTF_CTL_BURST		BIT(7)
+#define MEM_INTF_CTL_WR_EN		BIT(6)
+#define RIF_MEM_ACCESS_REQ		BIT(7)
+
+#define MEM_IF_TIMEOUT_MS		5000
+#define SRAM_ACCESS_RELEASE_DELAY_MS	500
+
+struct qcom_fg_chip;
+
+struct qcom_fg_ops {
+	int (*get_capacity)(struct qcom_fg_chip *chip, int *);
+	int (*get_temperature)(struct qcom_fg_chip *chip, int *);
+	int (*get_current)(struct qcom_fg_chip *chip, int *);
+	int (*get_voltage)(struct qcom_fg_chip *chip, int *);
+	int (*get_temp_threshold)(struct qcom_fg_chip *chip,
+			enum power_supply_property psp, int *);
+	int (*set_temp_threshold)(struct qcom_fg_chip *chip,
+			enum power_supply_property psp, int);
+
+	short memif_base;
+};
+
+struct qcom_fg_chip {
+	struct device *dev;
+	unsigned int base;
+	struct regmap *regmap;
+	const struct qcom_fg_ops *ops;
+	struct notifier_block nb;
+
+	struct power_supply *batt_psy;
+	struct power_supply_battery_info *batt_info;
+	struct power_supply *chg_psy;
+	int status;
+	struct delayed_work status_changed_work;
+
+	struct completion sram_access_granted;
+	struct completion sram_access_revoked;
+	struct workqueue_struct *sram_wq;
+	struct delayed_work sram_release_access_work;
+	spinlock_t sram_request_lock;
+	spinlock_t sram_rw_lock;
+	int sram_requests;
+};
+
+/************************
+ * IO FUNCTIONS
+ * **********************/
+
+/**
+ * @brief qcom_fg_read() - Read multiple registers with regmap_bulk_read
+ *
+ * @param chip Pointer to chip
+ * @param val Pointer to read values into
+ * @param addr Address to read from
+ * @param len Number of registers (bytes) to read
+ * @return int 0 on success, negative errno on error
+ */
+static int qcom_fg_read(struct qcom_fg_chip *chip, u8 *val, u16 addr, int len)
+{
+	if (((chip->base + addr) & 0xff00) == 0)
+		return -EINVAL;
+
+	dev_vdbg(chip->dev, "%s: Reading 0x%x bytes from 0x%x", __func__, len, addr);
+
+	return regmap_bulk_read(chip->regmap, chip->base + addr, val, len);
+}
+
+/**
+ * @brief qcom_fg_write() - Write multiple registers with regmap_bulk_write
+ *
+ * @param chip Pointer to chip
+ * @param val Pointer to write values from
+ * @param addr Address to write to
+ * @param len Number of registers (bytes) to write
+ * @return int 0 on success, negative errno on error
+ */
+static int qcom_fg_write(struct qcom_fg_chip *chip, u8 *val, u16 addr, int len)
+{
+	bool sec_access = (addr & 0xff) > 0xd0;
+	u8 sec_addr_val = 0xa5;
+	int ret;
+
+	if (((chip->base + addr) & 0xff00) == 0)
+			return -EINVAL;
+
+	dev_vdbg(chip->dev, "%s: Writing 0x%x to 0x%x", __func__, *val, addr);
+
+	if (sec_access) {
+		ret = regmap_bulk_write(chip->regmap,
+				((chip->base + addr) & 0xff00) | 0xd0,
+				&sec_addr_val, 1);
+		if (ret)
+			return ret;
+	}
+
+	return regmap_bulk_write(chip->regmap, chip->base + addr, val, len);
+}
+
+/**
+ * @brief qcom_fg_masked_write() - like qcom_fg_write but applies
+ * a mask first.
+ *
+ * @param chip Pointer to chip
+ * @param val Pointer to write values from
+ * @param addr Address to write to
+ * @param len Number of registers (bytes) to write
+ * @return int 0 on success, negative errno on error
+ */
+static int qcom_fg_masked_write(struct qcom_fg_chip *chip, u16 addr, u8 mask, u8 val)
+{
+	u8 reg;
+	int ret;
+
+	ret = qcom_fg_read(chip, &reg, addr, 1);
+	if (ret)
+		return ret;
+
+	reg &= ~mask;
+	reg |= val & mask;
+
+	return qcom_fg_write(chip, &reg, addr, 1);
+}
+
+/************************
+ * SRAM FUNCTIONS
+ * **********************/
+
+/**
+ * @brief qcom_fg_sram_check_access() - Check if SRAM is accessible
+ *
+ * @param chip Pointer to chip
+ * @return bool true if accessible, false otherwise
+ */
+static bool qcom_fg_sram_check_access(struct qcom_fg_chip *chip)
+{
+	u8 mem_if_status;
+	int ret;
+
+	ret = qcom_fg_read(chip, &mem_if_status,
+		MEM_INTF_STS(chip), 1);
+
+	if (ret || !(mem_if_status & MEM_INTF_AVAIL))
+		return false;
+
+	ret = qcom_fg_read(chip, &mem_if_status,
+		MEM_INTF_CFG(chip), 1);
+
+	if (ret)
+		return false;
+
+	return !!(mem_if_status & RIF_MEM_ACCESS_REQ);
+}
+
+/**
+ * @brief qcom_fg_sram_request_access() - Request access to SRAM and wait for it
+ *
+ * @param chip Pointer to chip
+ * @return int 0 on success, negative errno on error
+ */
+static int qcom_fg_sram_request_access(struct qcom_fg_chip *chip)
+{
+	bool sram_accessible;
+	int ret;
+
+	spin_lock(&chip->sram_request_lock);
+
+	sram_accessible = qcom_fg_sram_check_access(chip);
+
+	dev_vdbg(chip->dev, "Requesting SRAM access, current state: %d, requests: %d\n",
+		sram_accessible, chip->sram_requests);
+
+	if (!sram_accessible && chip->sram_requests == 0) {
+		ret = qcom_fg_masked_write(chip, MEM_INTF_CFG(chip),
+				RIF_MEM_ACCESS_REQ, RIF_MEM_ACCESS_REQ);
+		if (ret) {
+			dev_err(chip->dev,
+				"Failed to set SRAM access request bit: %d\n", ret);
+
+			spin_unlock(&chip->sram_request_lock);
+			return ret;
+		}
+	}
+
+	chip->sram_requests++;
+
+	spin_unlock(&chip->sram_request_lock);
+
+	/* Wait to get access to SRAM, and try again if interrupted */
+	do {
+		ret = wait_for_completion_interruptible_timeout(
+			&chip->sram_access_granted,
+			msecs_to_jiffies(MEM_IF_TIMEOUT_MS));
+	} while(ret == -ERESTARTSYS);
+
+	if (ret <= 0) {
+		ret = -ETIMEDOUT;
+
+		spin_lock(&chip->sram_request_lock);
+		chip->sram_requests--;
+		spin_unlock(&chip->sram_request_lock);
+	} else {
+		ret = 0;
+
+		reinit_completion(&chip->sram_access_revoked);
+	}
+
+	return ret;
+}
+
+/**
+ * @brief qcom_fg_sram_release_access() - Release access to SRAM
+ *
+ * @param chip Pointer to chip
+ * @return int 0 on success, negative errno on error
+ */
+static void qcom_fg_sram_release_access(struct qcom_fg_chip *chip)
+{
+	spin_lock(&chip->sram_request_lock);
+
+	chip->sram_requests--;
+
+	if(WARN(chip->sram_requests < 0,
+			"sram_requests=%d, cannot be negative! resetting to 0.\n",
+			chip->sram_requests))
+		chip->sram_requests = 0;
+
+	if(chip->sram_requests == 0)
+		/* Schedule access release */
+		queue_delayed_work(chip->sram_wq, &chip->sram_release_access_work,
+			msecs_to_jiffies(SRAM_ACCESS_RELEASE_DELAY_MS));
+
+	spin_unlock(&chip->sram_request_lock);
+}
+
+static void qcom_fg_sram_release_access_worker(struct work_struct *work)
+{
+	struct qcom_fg_chip *chip;
+	bool wait = false;
+	int ret;
+
+	chip = container_of(work, struct qcom_fg_chip, sram_release_access_work.work);
+
+	spin_lock(&chip->sram_request_lock);
+
+	/* Request access release if there are still no access requests */
+	if(chip->sram_requests == 0) {
+		qcom_fg_masked_write(chip, MEM_INTF_CFG(chip), RIF_MEM_ACCESS_REQ, 0);
+		wait = true;
+	}
+
+	spin_unlock(&chip->sram_request_lock);
+
+	if(!wait)
+		return;
+
+	/* Wait for SRAM access to be released, and try again if interrupted */
+	do {
+		ret = wait_for_completion_interruptible_timeout(
+			&chip->sram_access_revoked,
+			msecs_to_jiffies(MEM_IF_TIMEOUT_MS));
+	} while(ret == -ERESTARTSYS);
+
+	reinit_completion(&chip->sram_access_granted);
+}
+
+/**
+ * @brief qcom_fg_sram_config_access() - Configure access to SRAM
+ *
+ * @param chip Pointer to chip
+ * @param write 0 for read access, 1 for write access
+ * @param burst 1 to access mutliple addresses successively
+ * @return int 0 on success, negative errno on error
+ */
+static int qcom_fg_sram_config_access(struct qcom_fg_chip *chip,
+		bool write, bool burst)
+{
+	u8 intf_ctl;
+	int ret;
+
+	intf_ctl = (write ? MEM_INTF_CTL_WR_EN : 0)
+			| (burst ? MEM_INTF_CTL_BURST : 0);
+
+	ret = qcom_fg_write(chip, &intf_ctl,
+			MEM_INTF_CTL(chip), 1);
+	if (ret) {
+		dev_err(chip->dev, "Failed to configure SRAM access: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+/**
+ * @brief qcom_fg_sram_read() - Read data from SRAM
+ *
+ * @param chip Pointer to chip
+ * @param val Pointer to read values into
+ * @param addr Address to read from
+ * @param len Number of bytes to read
+ * @return int 0 on success, negative errno on error
+ */
+static int qcom_fg_sram_read(struct qcom_fg_chip *chip,
+		u8 *val, u16 addr, int len, int offset)
+{
+	u8 *rd_data = val;
+	int ret = 0;
+
+	ret = qcom_fg_sram_request_access(chip);
+	if (ret) {
+		dev_err(chip->dev, "Failed to request SRAM access: %d", ret);
+		return ret;
+	}
+
+	spin_lock(&chip->sram_rw_lock);
+
+	dev_vdbg(chip->dev,
+		"Reading address 0x%x with offset %d of length %d from SRAM",
+		addr, len, offset);
+
+	ret = qcom_fg_sram_config_access(chip, 0, (len > 4));
+	if (ret) {
+		dev_err(chip->dev, "Failed to configure SRAM access: %d", ret);
+		goto out;
+	}
+
+	while(len > 0) {
+		/* Set SRAM address register */
+		ret = qcom_fg_write(chip, (u8 *) &addr,
+				MEM_INTF_ADDR_LSB(chip), 2);
+		if (ret) {
+			dev_err(chip->dev, "Failed to set SRAM address: %d", ret);
+			goto out;
+		}
+
+		ret = qcom_fg_read(chip, rd_data,
+				MEM_INTF_RD_DATA0(chip) + offset, len);
+
+		addr += 4;
+
+		if (ret)
+			goto out;
+
+		rd_data += 4 - offset;
+		len -= 4 - offset;
+		offset = 0;
+	}
+out:
+	spin_unlock(&chip->sram_rw_lock);
+	qcom_fg_sram_release_access(chip);
+
+	return ret;
+}
+
+/**
+ * @brief qcom_fg_sram_write() - Write data to SRAM
+ *
+ * @param chip Pointer to chip
+ * @param val Pointer to write values from
+ * @param addr Address to write to
+ * @param len Number of bytes to write
+ * @return int 0 on success, negative errno on error
+ */
+static int qcom_fg_sram_write(struct qcom_fg_chip *chip,
+		u8 *val, u16 addr, int len, int offset)
+{
+	u8 *wr_data = val;
+	int ret;
+
+	ret = qcom_fg_sram_request_access(chip);
+	if (ret) {
+		dev_err(chip->dev, "Failed to request SRAM access: %d", ret);
+		return ret;
+	}
+
+	spin_lock(&chip->sram_rw_lock);
+
+	dev_vdbg(chip->dev,
+		"Wrtiting address 0x%x with offset %d of length %d to SRAM",
+		addr, len, offset);
+
+	ret = qcom_fg_sram_config_access(chip, 1, (len > 4));
+	if (ret) {
+		dev_err(chip->dev, "Failed to configure SRAM access: %d", ret);
+		goto out;
+	}
+
+	while(len > 0) {
+		/* Set SRAM address register */
+		ret = qcom_fg_write(chip, (u8 *) &addr,
+				MEM_INTF_ADDR_LSB(chip), 2);
+		if (ret) {
+			dev_err(chip->dev, "Failed to set SRAM address: %d", ret);
+			goto out;
+		}
+
+		ret = qcom_fg_write(chip, wr_data,
+				MEM_INTF_WR_DATA0(chip) + offset, len);
+
+		addr += 4;
+
+		if (ret)
+			goto out;
+
+		wr_data += 4 - offset;
+		len -= 4 - offset;
+		offset = 0;
+	}
+out:
+	spin_unlock(&chip->sram_rw_lock);
+	qcom_fg_sram_release_access(chip);
+
+	return ret;
+}
+
+/*************************
+ * BATTERY STATUS
+ * ***********************/
+
+/**
+ * @brief qcom_fg_get_capacity() - Get remaining capacity of battery
+ *
+ * @param chip Pointer to chip
+ * @param val Pointer to store value at
+ * @return int 0 on success, negative errno on error
+ */
+static int qcom_fg_get_capacity(struct qcom_fg_chip *chip, int *val)
+{
+	u8 cap[2];
+	int ret;
+
+	ret = qcom_fg_read(chip, cap, BATT_MONOTONIC_SOC, 2);
+	if (ret) {
+		dev_err(chip->dev, "Failed to read capacity: %d", ret);
+		return ret;
+	}
+
+	if (cap[0] != cap[1]) {
+		cap[0] = cap[0] < cap[1] ? cap[0] : cap[1];
+	}
+
+	*val = DIV_ROUND_CLOSEST((cap[0] - 1) * 98, 0xff - 2) + 1;
+
+	return 0;
+}
+
+/**
+ * @brief qcom_fg_get_temperature() - Get temperature of battery
+ *
+ * @param chip Pointer to chip
+ * @param val Pointer to store value at
+ * @return int 0 on success, negative errno on error
+ */
+static int qcom_fg_get_temperature(struct qcom_fg_chip *chip, int *val)
+{
+	int temp;
+	u8 readval[2];
+	int ret;
+
+	ret = qcom_fg_sram_read(chip, readval, BATT_TEMP, 2, 2);
+	if (ret) {
+		dev_err(chip->dev, "Failed to read temperature: %d", ret);
+		return ret;
+	}
+
+	temp = readval[1] << 8 | readval[0];
+	*val = temp * 625 / 1000 - 2730;
+	return 0;
+}
+
+/**
+ * @brief qcom_fg_get_current() - Get current being drawn from battery
+ *
+ * @param chip Pointer to chip
+ * @param val Pointer to store value at
+ * @return int 0 on success, negative errno on error
+ */
+static int qcom_fg_get_current(struct qcom_fg_chip *chip, int *val)
+{
+	s16 temp;
+	u8 readval[2];
+	int ret;
+
+	ret = qcom_fg_sram_read(chip, readval, BATT_VOLTAGE_CURRENT, 2, 3);
+	if (ret) {
+		dev_err(chip->dev, "Failed to read current: %d", ret);
+		return ret;
+	}
+
+	temp = (s16)(readval[1] << 8 | readval[0]);
+	*val = div_s64((s64)temp * 152587, 1000);
+
+	return 0;
+}
+
+/**
+ * @brief qcom_fg_get_voltage() - Get voltage of battery
+ *
+ * @param chip Pointer to chip
+ * @param val Pointer to store value at
+ * @return int 0 on success, negative errno on error
+ */
+static int qcom_fg_get_voltage(struct qcom_fg_chip *chip, int *val)
+{
+	int temp;
+	u8 readval[2];
+	int ret;
+
+	ret = qcom_fg_sram_read(chip, readval, BATT_VOLTAGE_CURRENT, 2, 1);
+	if (ret) {
+		dev_err(chip->dev, "Failed to read voltage: %d", ret);
+		return ret;
+	}
+
+	temp = readval[1] << 8 | readval[0];
+	*val = div_u64((u64)temp * 152587, 1000);
+
+	return 0;
+}
+
+/**
+ * @brief qcom_fg_get_temp_threshold() - Get configured temperature thresholds
+ *
+ * @param chip Pointer to chip
+ * @param psp Power supply property of temperature limit
+ * @param val Pointer to store value at
+ * @return int 0 on success, negative errno on error
+ */
+static int qcom_fg_get_temp_threshold(struct qcom_fg_chip *chip,
+				enum power_supply_property psp, int *val)
+{
+	u8 temp;
+	int offset;
+	int ret;
+
+	switch (psp) {
+	case POWER_SUPPLY_PROP_TEMP_MIN:
+		offset = 0;
+		break;
+	case POWER_SUPPLY_PROP_TEMP_MAX:
+		offset = 1;
+		break;
+	case POWER_SUPPLY_PROP_TEMP_ALERT_MIN:
+		offset = 2;
+		break;
+	case POWER_SUPPLY_PROP_TEMP_ALERT_MAX:
+		offset = 3;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	ret = qcom_fg_sram_read(chip, &temp, TEMP_THRESHOLD, 1, offset);
+	if (ret < 0) {
+		dev_err(chip->dev, "Failed to read JEITA property %d level: %d\n", psp, ret);
+		return ret;
+	}
+
+	*val = (temp - 30) * 10;
+
+	return 0;
+}
+
+/**
+ * @brief qcom_fg_set_temp_threshold() - Configure temperature thresholds
+ *
+ * @param chip Pointer to chip
+ * @param psp Power supply property of temperature limit
+ * @param val Pointer to get value from
+ * @return int 0 on success, negative errno on error
+ */
+static int qcom_fg_set_temp_threshold(struct qcom_fg_chip *chip,
+				enum power_supply_property psp, int val)
+{
+	u8 temp;
+	int offset;
+	int ret;
+
+	switch (psp) {
+	case POWER_SUPPLY_PROP_TEMP_MIN:
+		offset = 0;
+		break;
+	case POWER_SUPPLY_PROP_TEMP_MAX:
+		offset = 1;
+		break;
+	case POWER_SUPPLY_PROP_TEMP_ALERT_MIN:
+		offset = 2;
+		break;
+	case POWER_SUPPLY_PROP_TEMP_ALERT_MAX:
+		offset = 3;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	temp = val / 10 + 30;
+
+	ret = qcom_fg_sram_write(chip, &temp, TEMP_THRESHOLD, 1, offset);
+	if (ret < 0) {
+		dev_err(chip->dev, "Failed to write JEITA property %d level: %d\n", psp, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+/*************************
+ * BATTERY STATUS, GEN3
+ * ***********************/
+
+/**
+ * @brief qcom_fg_gen3_get_temperature() - Get temperature of battery
+ *
+ * @param chip Pointer to chip
+ * @param val Pointer to store value at
+ * @return int 0 on success, negative errno on error
+ */
+static int qcom_fg_gen3_get_temperature(struct qcom_fg_chip *chip, int *val)
+{
+	int temp;
+	u8 readval[2];
+	int ret;
+
+	ret = qcom_fg_read(chip, readval, PARAM_ADDR_BATT_TEMP, 2);
+	if (ret) {
+		dev_err(chip->dev, "Failed to read temperature: %d\n", ret);
+		return ret;
+	}
+
+	temp = ((readval[1] & BATT_TEMP_MSB_MASK) << 8) |
+		(readval[0] & BATT_TEMP_LSB_MASK);
+	temp = DIV_ROUND_CLOSEST(temp * 10, 4);
+
+	*val = temp -2730;
+	return 0;
+}
+
+/**
+ * @brief qcom_fg_gen3_get_current() - Get current being drawn from battery
+ *
+ * @param chip Pointer to chip
+ * @param val Pointer to store value at
+ * @return int 0 on success, negative errno on error
+ */
+static int qcom_fg_gen3_get_current(struct qcom_fg_chip *chip, int *val)
+{
+	s16 temp;
+	u8 readval[2];
+	int ret;
+
+	ret = qcom_fg_read(chip, readval, PARAM_ADDR_BATT_CURRENT, 2);
+	if (ret) {
+		dev_err(chip->dev, "Failed to read current: %d\n", ret);
+		return ret;
+	}
+
+	//handle rev 1 too
+	temp = (s16)(readval[1] << 8 | readval[0]);
+	*val = div_s64((s64)temp * 488281, 1000);
+
+	/*
+	 * The power supply API expects charging batteries to report a
+	 * positive current, which is inverted from what the PMIC reports.
+	 */
+	*val = -*val;
+
+	return 0;
+}
+
+/**
+ * @brief qcom_fg_gen3_get_voltage() - Get voltage of battery
+ *
+ * @param chip Pointer to chip
+ * @param val Pointer to store value at
+ * @return int 0 on success, negative errno on error
+ */
+static int qcom_fg_gen3_get_voltage(struct qcom_fg_chip *chip, int *val)
+{
+	int temp;
+	u8 readval[2];
+	int ret;
+
+	ret = qcom_fg_read(chip, readval, PARAM_ADDR_BATT_VOLTAGE, 2);
+	if (ret) {
+		dev_err(chip->dev, "Failed to read voltage: %d\n", ret);
+		return ret;
+	}
+
+	//handle rev 1 too
+	temp = readval[1] << 8 | readval[0];
+	*val = div_u64((u64)temp * 122070, 1000);
+	return 0;
+}
+
+/**
+ * @brief qcom_fg_gen3_get_temp_threshold() - Get configured temperature thresholds
+ *
+ * @param chip Pointer to chip
+ * @param psp Power supply property of temperature limit
+ * @param val Pointer to store value at
+ * @return int 0 on success, negative errno on error
+ */
+static int qcom_fg_gen3_get_temp_threshold(struct qcom_fg_chip *chip,
+				enum power_supply_property psp, int *val)
+{
+	u8 temp;
+	u16 reg;
+	int ret;
+
+	switch (psp) {
+	case POWER_SUPPLY_PROP_TEMP_MIN:
+		reg = BATT_INFO_JEITA_COLD;
+		break;
+	case POWER_SUPPLY_PROP_TEMP_MAX:
+		reg = BATT_INFO_JEITA_HOT;
+		break;
+	case POWER_SUPPLY_PROP_TEMP_ALERT_MIN:
+		reg = BATT_INFO_JEITA_COOL;
+		break;
+	case POWER_SUPPLY_PROP_TEMP_ALERT_MAX:
+		reg = BATT_INFO_JEITA_WARM;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	ret = qcom_fg_read(chip, &temp, reg, 1);
+	if (ret < 0) {
+		dev_err(chip->dev, "Failed to read JEITA property %d level: %d\n", psp, ret);
+		return ret;
+	}
+
+	/* Resolution is 0.5C. Base is -30C. */
+	*val = (((5 * temp) / 10) - 30) * 10;
+	return 0;
+}
+
+/*************************
+ * BATTERY STATUS, GEN4
+ * ***********************/
+
+/**
+ * @brief qcom_fg_gen4_get_temperature() - Get temperature of battery
+ *
+ * @param chip Pointer to chip
+ * @param val Pointer to store value at
+ * @return int 0 on success, negative errno on error
+ */
+static int qcom_fg_gen4_get_temperature(struct qcom_fg_chip *chip, int *val)
+{
+	int temp;
+	u8 readval[2];
+	int ret;
+
+	ret = qcom_fg_read(chip, readval, ADC_RR_BATT_TEMP_LSB, 2);
+	if (ret) {
+		dev_err(chip->dev, "Failed to read temperature: %d", ret);
+		return ret;
+	}
+
+	temp = readval[1] << 8 | readval[0];
+	*val = temp * 10;
+	return 0;
+}
+
+/************************
+ * BATTERY POWER SUPPLY
+ * **********************/
+
+/* Pre-Gen3 fuel gauge. PMI8996 and older */
+static const struct qcom_fg_ops ops_fg = {
+	.get_capacity = qcom_fg_get_capacity,
+	.get_temperature = qcom_fg_get_temperature,
+	.get_current = qcom_fg_get_current,
+	.get_voltage = qcom_fg_get_voltage,
+	.get_temp_threshold = qcom_fg_get_temp_threshold,
+	.set_temp_threshold = qcom_fg_set_temp_threshold,
+	.memif_base = 0x400,
+};
+
+/* Gen3 fuel gauge. PMI8998 and newer */
+static const struct qcom_fg_ops ops_fg_gen3 = {
+	.get_capacity = qcom_fg_get_capacity,
+	.get_temperature = qcom_fg_gen3_get_temperature,
+	.get_current = qcom_fg_gen3_get_current,
+	.get_voltage = qcom_fg_gen3_get_voltage,
+	.get_temp_threshold = qcom_fg_gen3_get_temp_threshold,
+	.memif_base = 0x400,
+};
+
+/* Gen4 fuel gauge. PM8150B and newer */
+static const struct qcom_fg_ops ops_fg_gen4 = {
+	.get_capacity = qcom_fg_get_capacity,
+	.get_temperature = qcom_fg_gen4_get_temperature,
+	.get_current = qcom_fg_gen3_get_current,
+	.get_voltage = qcom_fg_gen3_get_voltage,
+	.get_temp_threshold = qcom_fg_gen3_get_temp_threshold,
+	.memif_base = 0x300,
+};
+
+static enum power_supply_property qcom_fg_props[] = {
+	POWER_SUPPLY_PROP_STATUS,
+	POWER_SUPPLY_PROP_TECHNOLOGY,
+	POWER_SUPPLY_PROP_CAPACITY,
+	POWER_SUPPLY_PROP_CURRENT_NOW,
+	POWER_SUPPLY_PROP_VOLTAGE_NOW,
+	POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN,
+	POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN,
+	POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN,
+	POWER_SUPPLY_PROP_PRESENT,
+	POWER_SUPPLY_PROP_TEMP,
+	POWER_SUPPLY_PROP_TEMP_MIN,
+	POWER_SUPPLY_PROP_TEMP_MAX,
+	POWER_SUPPLY_PROP_TEMP_ALERT_MIN,
+	POWER_SUPPLY_PROP_TEMP_ALERT_MAX,
+};
+
+static int qcom_fg_get_property(struct power_supply *psy,
+		enum power_supply_property psp,
+		union power_supply_propval *val)
+{
+	struct qcom_fg_chip *chip = power_supply_get_drvdata(psy);
+	int temp, ret = 0;
+
+	dev_dbg(chip->dev, "Getting property: %d", psp);
+
+	switch (psp) {
+	case POWER_SUPPLY_PROP_STATUS:
+		/* Get status from charger if available */
+		if (chip->chg_psy &&
+			chip->status != POWER_SUPPLY_STATUS_UNKNOWN) {
+			val->intval = chip->status;
+			break;
+		} else {
+			/*
+			 * Fall back to capacity and current-based
+			 * status checking
+			 */
+			ret = chip->ops->get_capacity(chip, &temp);
+			if (ret) {
+				val->intval = POWER_SUPPLY_STATUS_UNKNOWN;
+				break;
+			}
+			if (temp == 100) {
+				val->intval = POWER_SUPPLY_STATUS_FULL;
+				break;
+			}
+
+			ret = chip->ops->get_current(chip, &temp);
+			if (ret) {
+				val->intval = POWER_SUPPLY_STATUS_UNKNOWN;
+				break;
+			}
+			if (temp > 0)
+				val->intval = POWER_SUPPLY_STATUS_CHARGING;
+			else if (temp < 0)
+				val->intval = POWER_SUPPLY_STATUS_DISCHARGING;
+			else
+				val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING;
+		}
+
+		break;
+	case POWER_SUPPLY_PROP_TECHNOLOGY:
+		val->intval = POWER_SUPPLY_TECHNOLOGY_LION;
+		break;
+	case POWER_SUPPLY_PROP_CAPACITY:
+		ret = chip->ops->get_capacity(chip, &val->intval);
+		break;
+	case POWER_SUPPLY_PROP_CURRENT_NOW:
+		ret = chip->ops->get_current(chip, &val->intval);
+		break;
+	case POWER_SUPPLY_PROP_VOLTAGE_NOW:
+		ret = chip->ops->get_voltage(chip, &val->intval);
+		break;
+	case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN:
+		val->intval = chip->batt_info->voltage_min_design_uv;
+		break;
+	case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN:
+		val->intval = chip->batt_info->voltage_max_design_uv;
+		break;
+	case POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN:
+		val->intval = chip->batt_info->charge_full_design_uah;
+		break;
+	case POWER_SUPPLY_PROP_PRESENT:
+		val->intval = 1;
+		break;
+	case POWER_SUPPLY_PROP_TEMP:
+		ret = chip->ops->get_temperature(chip, &val->intval);
+		break;
+	case POWER_SUPPLY_PROP_TEMP_MIN:
+	case POWER_SUPPLY_PROP_TEMP_MAX:
+	case POWER_SUPPLY_PROP_TEMP_ALERT_MIN:
+	case POWER_SUPPLY_PROP_TEMP_ALERT_MAX:
+		ret = chip->ops->get_temp_threshold(chip, psp, &val->intval);
+		break;
+	default:
+		dev_err(chip->dev, "invalid property: %d\n", psp);
+		return -EINVAL;
+	}
+
+	return ret;
+}
+
+static const struct power_supply_desc batt_psy_desc = {
+	.name = "qcom-battery",
+	.type = POWER_SUPPLY_TYPE_BATTERY,
+	.properties = qcom_fg_props,
+	.num_properties = ARRAY_SIZE(qcom_fg_props),
+	.get_property = qcom_fg_get_property,
+};
+
+/********************
+ * INIT FUNCTIONS
+ * ******************/
+
+static int qcom_fg_iacs_clear_sequence(struct qcom_fg_chip *chip)
+{
+	u8 temp;
+	int ret;
+
+	/* clear the error */
+	ret = qcom_fg_masked_write(chip, MEM_INTF_IMA_CFG(chip), BIT(2), BIT(2));
+	if (ret) {
+		dev_err(chip->dev, "Failed to write IMA_CFG: %d\n", ret);
+		return ret;
+	}
+
+	temp = 0x4;
+	ret = qcom_fg_write(chip, &temp, MEM_INTF_ADDR_LSB(chip) + 1, 1);
+	if (ret) {
+		dev_err(chip->dev, "Failed to write MEM_INTF_ADDR_MSB: %d\n", ret);
+		return ret;
+	}
+
+	temp = 0x0;
+	ret = qcom_fg_write(chip, &temp, MEM_INTF_WR_DATA0(chip) + 3, 1);
+	if (ret) {
+		dev_err(chip->dev, "Failed to write WR_DATA3: %d\n", ret);
+		return ret;
+	}
+
+	ret = qcom_fg_read(chip, &temp, MEM_INTF_RD_DATA0(chip) + 3, 1);
+	if (ret) {
+		dev_err(chip->dev, "Failed to write RD_DATA3: %d\n", ret);
+		return ret;
+	}
+
+	ret = qcom_fg_masked_write(chip, MEM_INTF_IMA_CFG(chip), BIT(2), 0);
+	if (ret) {
+		dev_err(chip->dev, "Failed to write IMA_CFG: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int qcom_fg_clear_ima(struct qcom_fg_chip *chip,
+		bool check_hw_sts)
+{
+	u8 err_sts, exp_sts, hw_sts;
+	bool run_err_clr_seq = false;
+	int ret;
+
+	ret = qcom_fg_read(chip, &err_sts,
+			MEM_INTF_IMA_ERR_STS(chip), 1);
+	if (ret) {
+		dev_err(chip->dev, "Failed to read IMA_ERR_STS: %d\n", ret);
+		return ret;
+	}
+
+	ret = qcom_fg_read(chip, &exp_sts,
+			MEM_INTF_IMA_EXP_STS(chip), 1);
+	if (ret) {
+		dev_err(chip->dev, "Failed to read IMA_EXP_STS: %d\n", ret);
+		return ret;
+	}
+
+	if (check_hw_sts) {
+		ret = qcom_fg_read(chip, &hw_sts,
+				MEM_INTF_IMA_HW_STS(chip), 1);
+		if (ret) {
+			dev_err(chip->dev, "Failed to read IMA_HW_STS: %d\n", ret);
+			return ret;
+		}
+		/*
+		 * Lower nibble should be equal to upper nibble before SRAM
+		 * transactions begins from SW side.
+		 */
+		if ((hw_sts & 0x0f) != hw_sts >> 4) {
+			dev_dbg(chip->dev, "IMA HW not in correct state, hw_sts=%x\n",
+					hw_sts);
+			run_err_clr_seq = true;
+		}
+	}
+
+	if (exp_sts & (BIT(0) | BIT(1) | BIT(3) |
+		BIT(4) | BIT(5) | BIT(6) |
+		BIT(7))) {
+		dev_dbg(chip->dev, "IMA exception bit set, exp_sts=%x\n", exp_sts);
+		run_err_clr_seq = true;
+	}
+
+	if (run_err_clr_seq) {
+		ret = qcom_fg_iacs_clear_sequence(chip);
+		if (!ret)
+			return -EAGAIN;
+	}
+
+	return 0;
+}
+
+irqreturn_t qcom_fg_handle_soc_delta(int irq, void *data)
+{
+	struct qcom_fg_chip *chip = data;
+
+	/* Signal change in state of charge */
+	power_supply_changed(chip->batt_psy);
+	dev_dbg(chip->dev, "SOC changed");
+
+	return IRQ_HANDLED;
+}
+
+irqreturn_t qcom_fg_handle_mem_avail(int irq, void *data)
+{
+	struct qcom_fg_chip *chip = data;
+
+	if (qcom_fg_sram_check_access(chip)) {
+		complete_all(&chip->sram_access_granted);
+		dev_dbg(chip->dev, "SRAM access granted");
+	} else {
+		complete_all(&chip->sram_access_revoked);
+		dev_dbg(chip->dev, "SRAM access revoked");
+	}
+
+	return IRQ_HANDLED;
+}
+
+static void qcom_fg_status_changed_worker(struct work_struct *work)
+{
+	struct qcom_fg_chip *chip = container_of(work, struct qcom_fg_chip,
+						status_changed_work.work);
+
+	power_supply_changed(chip->batt_psy);
+}
+
+static int qcom_fg_notifier_call(struct notifier_block *nb,
+		unsigned long val, void *v)
+{
+	struct qcom_fg_chip *chip = container_of(nb, struct qcom_fg_chip, nb);
+	struct power_supply *psy = v;
+	union power_supply_propval propval;
+	int ret;
+
+	if (psy == chip->chg_psy) {
+		ret = power_supply_get_property(psy,
+				POWER_SUPPLY_PROP_STATUS, &propval);
+		if (ret)
+			chip->status = POWER_SUPPLY_STATUS_UNKNOWN;
+
+		chip->status = propval.intval;
+
+		power_supply_changed(chip->batt_psy);
+
+		if (chip->status == POWER_SUPPLY_STATUS_UNKNOWN) {
+			/*
+			 * REVISIT: Find better solution or remove current-based
+			 * status checking once checking is properly implemented
+			 * in charger drivers
+
+			 * Sometimes it take a while for current to stabilize,
+			 * so signal property change again later to make sure
+			 * current-based status is properly detected.
+			 */
+			cancel_delayed_work_sync(&chip->status_changed_work);
+			schedule_delayed_work(&chip->status_changed_work,
+						msecs_to_jiffies(1000));
+		}
+	}
+
+	return NOTIFY_OK;
+}
+
+static int qcom_fg_probe(struct platform_device *pdev)
+{
+	struct power_supply_config supply_config = {};
+	struct qcom_fg_chip *chip;
+	const __be32 *prop_addr;
+	int irq;
+	u8 dma_status;
+	bool error_present;
+	int ret;
+
+	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
+	if (!chip)
+		return -ENOMEM;
+
+	chip->dev = &pdev->dev;
+	chip->ops = of_device_get_match_data(&pdev->dev);
+
+	chip->regmap = dev_get_regmap(pdev->dev.parent, NULL);
+	if (!chip->regmap) {
+		dev_err(chip->dev, "Failed to locate the regmap\n");
+		return -ENODEV;
+	}
+
+	/* Get base address */
+	prop_addr = of_get_address(pdev->dev.of_node, 0, NULL, NULL);
+	if (!prop_addr) {
+		dev_err(chip->dev, "Failed to read SOC base address from dt\n");
+		return -EINVAL;
+	}
+	chip->base = be32_to_cpu(*prop_addr);
+
+	/*
+	 * Change the FG_MEM_INT interrupt to track IACS_READY
+	 * condition instead of end-of-transaction. This makes sure
+	 * that the next transaction starts only after the hw is ready.
+	 * IACS_INTR_SRC_SLCT is BIT(3)
+	 */
+	ret = qcom_fg_masked_write(chip,
+		MEM_INTF_IMA_CFG(chip), BIT(3), BIT(3));
+	if (ret) {
+		dev_err(chip->dev,
+			"Failed to configure interrupt sourete: %d\n", ret);
+		return ret;
+	}
+
+	ret = qcom_fg_clear_ima(chip, true);
+	if (ret && ret != -EAGAIN) {
+		dev_err(chip->dev, "Failed to clear IMA exception: %d\n", ret);
+		return ret;
+	}
+
+	/* Check and clear DMA errors */
+	ret = qcom_fg_read(chip, &dma_status, MEM_IF_DMA_STS(chip), 1);
+	if (ret < 0) {
+		dev_err(chip->dev, "Failed to read dma_status: %d\n", ret);
+		return ret;
+	}
+
+	error_present = dma_status & (BIT(1) | BIT(2));
+	ret = qcom_fg_masked_write(chip, MEM_IF_DMA_CTL(chip), BIT(0),
+			error_present ? BIT(0) : 0);
+	if (ret < 0) {
+		dev_err(chip->dev, "Failed to write dma_ctl: %d\n", ret);
+		return ret;
+	}
+
+	supply_config.drv_data = chip;
+	supply_config.fwnode = pdev->dev.fwnode;
+
+	chip->batt_psy = devm_power_supply_register(chip->dev,
+			&batt_psy_desc, &supply_config);
+	if (IS_ERR(chip->batt_psy)) {
+		if (PTR_ERR(chip->batt_psy) != -EPROBE_DEFER)
+			dev_err(&pdev->dev, "Failed to register battery\n");
+		return PTR_ERR(chip->batt_psy);
+	}
+
+	platform_set_drvdata(pdev, chip);
+
+	ret = power_supply_get_battery_info(chip->batt_psy, &chip->batt_info);
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to get battery info: %d\n", ret);
+		return ret;
+	}
+
+	/* Initialize SRAM */
+	if (of_device_is_compatible(pdev->dev.of_node, "qcom,pmi8994-fg")) {
+		irq = of_irq_get_byname(pdev->dev.of_node, "mem-avail");
+		if (irq < 0) {
+			dev_err(&pdev->dev, "Failed to get irq mem-avail byname: %d\n",
+				irq);
+			return irq;
+		}
+
+		init_completion(&chip->sram_access_granted);
+		init_completion(&chip->sram_access_revoked);
+
+		chip->sram_wq = create_singlethread_workqueue("qcom_fg");
+		INIT_DELAYED_WORK(&chip->sram_release_access_work,
+			qcom_fg_sram_release_access_worker);
+
+		ret = devm_request_threaded_irq(chip->dev, irq, NULL,
+						qcom_fg_handle_mem_avail,
+						IRQF_ONESHOT, "mem-avail", chip);
+		if (ret < 0) {
+			dev_err(&pdev->dev, "Failed to request mem-avail IRQ: %d\n", ret);
+			return ret;
+		}
+
+		spin_lock_init(&chip->sram_request_lock);
+		spin_lock_init(&chip->sram_rw_lock);
+		chip->sram_requests = 0;
+	}
+
+	/* Set default temperature thresholds */
+	if (chip->ops->set_temp_threshold) {
+		ret = chip->ops->set_temp_threshold(chip,
+						POWER_SUPPLY_PROP_TEMP_MIN,
+						BATT_TEMP_JEITA_COLD);
+		if (ret) {
+			dev_err(chip->dev,
+				"Failed to set cold threshold: %d\n", ret);
+			return ret;
+		}
+
+		ret = chip->ops->set_temp_threshold(chip,
+						POWER_SUPPLY_PROP_TEMP_MAX,
+						BATT_TEMP_JEITA_WARM);
+		if (ret) {
+			dev_err(chip->dev,
+				"Failed to set warm threshold: %d\n", ret);
+			return ret;
+		}
+
+		ret = chip->ops->set_temp_threshold(chip,
+						POWER_SUPPLY_PROP_TEMP_ALERT_MIN,
+						BATT_TEMP_JEITA_COOL);
+		if (ret) {
+			dev_err(chip->dev,
+				"Failed to set cool threshold: %d\n", ret);
+			return ret;
+		}
+
+		ret = chip->ops->set_temp_threshold(chip,
+						POWER_SUPPLY_PROP_TEMP_ALERT_MAX,
+						BATT_TEMP_JEITA_HOT);
+		if (ret) {
+			dev_err(chip->dev,
+				"Failed to set hot threshold: %d\n", ret);
+			return ret;
+		}
+	}
+
+	/* Get soc-delta IRQ */
+	irq = of_irq_get_byname(pdev->dev.of_node, "soc-delta");
+	if (irq < 0) {
+		dev_err(&pdev->dev, "Failed to get irq soc-delta byname: %d\n",
+			irq);
+		return irq;
+	}
+
+	ret = devm_request_threaded_irq(chip->dev, irq, NULL,
+					qcom_fg_handle_soc_delta,
+					IRQF_ONESHOT, "soc-delta", chip);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "Failed to request soc-delta IRQ: %d\n", ret);
+		return ret;
+	}
+
+	/* Optional: Get charger power supply for status checking */
+	chip->chg_psy = power_supply_get_by_name("power-supplies");
+	if (IS_ERR(chip->chg_psy)) {
+		ret = PTR_ERR(chip->chg_psy);
+		dev_warn(chip->dev, "Failed to get charger supply: %d\n", ret);
+		chip->chg_psy = NULL;
+	}
+
+	if (chip->chg_psy) {
+		INIT_DELAYED_WORK(&chip->status_changed_work,
+			qcom_fg_status_changed_worker);
+
+		chip->nb.notifier_call = qcom_fg_notifier_call;
+		ret = power_supply_reg_notifier(&chip->nb);
+		if (ret) {
+			dev_err(chip->dev,
+				"Failed to register notifier: %d\n", ret);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static void qcom_fg_remove(struct platform_device *pdev)
+{
+	struct qcom_fg_chip *chip = platform_get_drvdata(pdev);
+
+	power_supply_put_battery_info(chip->batt_psy, chip->batt_info);
+
+	if(chip->sram_wq)
+		destroy_workqueue(chip->sram_wq);
+
+	return;
+}
+
+static const struct of_device_id fg_match_id_table[] = {
+	{ .compatible = "qcom,pmi8994-fg", .data = &ops_fg },
+	{ .compatible = "qcom,pmi8998-fg", .data = &ops_fg_gen3 },
+	{ .compatible = "qcom,pm8150b-fg", .data = &ops_fg_gen4 },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, fg_match_id_table);
+
+static struct platform_driver qcom_fg_driver = {
+	.probe = qcom_fg_probe,
+	.remove = qcom_fg_remove,
+	.driver = {
+		.name = "qcom-fg",
+		.of_match_table = fg_match_id_table,
+	},
+};
+
+module_platform_driver(qcom_fg_driver);
+
+MODULE_AUTHOR("Caleb Connolly <caleb@connolly.tech>");
+MODULE_AUTHOR("Joel Selvaraj <jo@jsfamily.in>");
+MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>");
+MODULE_DESCRIPTION("Qualcomm PMIC Fuel Gauge Driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/power/supply/qcom_pm8150b_charger.c b/drivers/power/supply/qcom_pm8150b_charger.c
new file mode 100644
index 000000000000..e1437eca8579
--- /dev/null
+++ b/drivers/power/supply/qcom_pm8150b_charger.c
@@ -0,0 +1,964 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2024, Teguh Sobirin <teguh@sobir.in>.
+ *
+ * This driver is for the switch-mode battery charger power delivery
+ * and boost hardware found in pm8150b and related PMICs.
+ * This work based on pmi8998 charger driver by
+ * Caleb Connolly <caleb.connolly@linaro.org>
+ * Should be merged with the existing charger driver in the future.
+ */
+
+#include <linux/bits.h>
+#include <linux/devm-helpers.h>
+#include <linux/iio/consumer.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/minmax.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pm_wakeirq.h>
+#include <linux/of.h>
+#include <linux/power_supply.h>
+#include <linux/regmap.h>
+#include <linux/types.h>
+#include <linux/workqueue.h>
+
+/* clang-format off */
+#define BATTERY_CHARGER_STATUS_1			0x06
+#define ICL_INCR_REQ_FOR_PRECHG_BIT			BIT(7)
+#define ZERO_CHARGE_CURRENT_BIT				BIT(6)
+#define STEP_CHARGING_STATUS_SHIFT			3
+#define STEP_CHARGING_STATUS_MASK			GENMASK(5, 3)
+#define BATTERY_CHARGER_STATUS_MASK			GENMASK(2, 0)
+
+#define BATTERY_CHARGER_STATUS_2			0x07
+#define DROP_IN_BATTERY_VOLTAGE_REFERENCE_BIT		BIT(7)
+#define VBATT_LTET_RECHARGE_BIT				BIT(6)
+#define VBATT_GTET_INHIBIT_BIT				BIT(5)
+#define VBATT_GTET_FLOAT_VOLTAGE_BIT			BIT(4)
+#define BATT_GT_FULL_ON_BIT				BIT(3)
+#define CHARGER_ERROR_STATUS_SFT_EXPIRE_BIT		BIT(2)
+#define CHARGER_ERROR_STATUS_BAT_OV_BIT			BIT(1)
+#define CHARGER_ERROR_STATUS_BAT_TERM_MISSING_BIT	BIT(0)
+
+#define BATTERY_CHARGER_STATUS_4		0x0A
+#define CHARGE_CURRENT_REFERENCE_MASK		GENMASK(7, 0)
+
+#define BATTERY_CHARGER_STATUS_7_REG		0x0D
+#define BAT_TEMP_STATUS_SOFT_LIMIT_MASK		GENMASK(5, 4)
+#define BAT_TEMP_STATUS_HOT_SOFT_BIT		BIT(5)
+#define BAT_TEMP_STATUS_COLD_SOFT_BIT		BIT(4)
+#define BAT_TEMP_STATUS_HARD_LIMIT_MASK		GENMASK(3, 2)
+#define BAT_TEMP_STATUS_TOO_HOT_BIT		BIT(3)
+#define BAT_TEMP_STATUS_TOO_COLD_BIT		BIT(2)
+#define BAT_TEMP_STATUS_TOO_HOT_AFP_BIT		BIT(1)
+#define BAT_TEMP_STATUS_TOO_COLD_AFP_BIT	BIT(0)
+
+#define CHARGING_ENABLE_CMD			0x42
+#define CHARGING_ENABLE_CMD_BIT			BIT(0)
+#define CHARGING_ENABLE_POF_BIT			BIT(1)
+
+#define CHGR_CFG2				0x51
+#define EN_FAVOR_IN_BIT				BIT(5)
+#define BAT_OV_ECC_BIT				BIT(4)
+#define I_TERM_BIT				BIT(3)
+#define AUTO_RECHG_BIT				BIT(2)
+#define SOC_BASED_RECHG_BIT			BIT(1)
+#define CHARGER_INHIBIT_BIT			BIT(0)
+
+#define PRE_CHARGE_CURRENT_CFG			0x60
+#define PRE_CHARGE_CURRENT_SETTING_MASK		GENMASK(2, 0)
+
+#define FAST_CHARGE_CURRENT_CFG			0x61
+#define FAST_CHARGE_CURRENT_SETTING_MASK	GENMASK(7, 0)
+
+#define FLOAT_VOLTAGE_CFG			0x70
+#define FLOAT_VOLTAGE_SETTING_MASK		GENMASK(7, 0)
+
+#define CHARGE_RCHG_SOC_THRESHOLD_CFG_REG	0x7D
+#define CHARGE_RCHG_SOC_THRESHOLD_CFG_MASK	GENMASK(7, 0)
+
+#define ICL_STATUS				0x107
+#define ICL_INPUT_CURRENT_LIMIT_MASK		GENMASK(7, 0)
+
+#define AICL_STATUS				0x108
+#define AICL_INPUT_CURRENT_LIMIT_MASK		GENMASK(7, 0)
+
+#define POWER_PATH_STATUS				0x10B
+#define P_PATH_INPUT_SS_DONE_BIT			BIT(7)
+#define P_PATH_USBIN_SUSPEND_STS_BIT			BIT(6)
+#define P_PATH_DCIN_SUSPEND_STS_BIT			BIT(5)
+#define P_PATH_USE_USBIN_BIT				BIT(4)
+#define P_PATH_USE_DCIN_BIT				BIT(3)
+#define P_PATH_POWER_PATH_MASK				GENMASK(2, 1)
+#define P_PATH_VALID_INPUT_POWER_SOURCE_STS_BIT		BIT(0)
+
+#define OTG_CFG					0x153
+#define OTG_RESERVED_BIT			BIT(7)
+#define FAST_ROLE_SWAP_START_OPTION_BIT		BIT(6)
+#define DIS_OTG_ON_TSD_BIT			BIT(5)
+#define OTG_CFG_4_BIT				BIT(4)
+#define EN_SOC_BASED_OTG_UVLO_BIT		BIT(3)
+#define ENABLE_OTG_IN_DEBUG_MODE_BIT		BIT(2)
+#define OTG_EN_SRC_CFG_BIT			BIT(1)
+#define OTG_HICCUP_CNTR_RST_TIMER_SEL_BIT	BIT(0)
+
+#define APSD_STATUS				0x307
+#define APSD_STATUS_7_BIT			BIT(7)
+#define HVDCP_CHECK_TIMEOUT_BIT			BIT(6)
+#define SLOW_PLUGIN_TIMEOUT_BIT			BIT(5)
+#define ENUMERATION_DONE_BIT			BIT(4)
+#define VADP_CHANGE_DONE_AFTER_AUTH_BIT		BIT(3)
+#define QC_AUTH_DONE_STATUS_BIT			BIT(2)
+#define QC_CHARGER_BIT				BIT(1)
+#define APSD_DTC_STATUS_DONE_BIT		BIT(0)
+
+#define APSD_RESULT_STATUS			0x308
+#define APSD_RESULT_STATUS_7_BIT		BIT(7)
+#define APSD_RESULT_STATUS_MASK			GENMASK(6, 0)
+#define QC_3P0_BIT				BIT(6)
+#define QC_2P0_BIT				BIT(5)
+#define FLOAT_CHARGER_BIT			BIT(4)
+#define DCP_CHARGER_BIT				BIT(3)
+#define CDP_CHARGER_BIT				BIT(2)
+#define OCP_CHARGER_BIT				BIT(1)
+#define SDP_CHARGER_BIT				BIT(0)
+
+#define USBIN_INT_RT_STS_OFFSET			0x310
+#define USBIN_PLUGIN_RT_STS_BIT			BIT(4)
+
+#define USBIN_CMD_IL				0x340
+#define USBIN_SUSPEND_BIT			BIT(0)
+
+#define CMD_APSD				0x341
+#define APSD_RERUN_BIT				BIT(0)
+
+#define CMD_ICL_OVERRIDE			0x342
+#define ICL_OVERRIDE_BIT			BIT(0)
+
+#define TYPE_C_CFG				0x358
+#define BC1P2_START_ON_CC_BIT			BIT(7)
+
+#define HVDCP_PULSE_COUNT_MAX			0x35b
+#define HVDCP_PULSE_COUNT_MAX_QC2_MASK		GENMASK(7, 6)
+
+#define USBIN_ADAPTER_ALLOW_CFG			0x360
+#define USBIN_ADAPTER_ALLOW_MASK		GENMASK(3, 0)
+
+#define USBIN_OPTIONS_1_CFG			0x362
+#define HVDCP_AUTH_ALG_EN_CFG_BIT		BIT(6)
+#define HVDCP_AUTONOMOUS_MODE_EN_CFG_BIT	BIT(5)
+#define BC1P2_SRC_DETECT_BIT			BIT(3)
+#define HVDCP_EN_BIT				BIT(2)
+#define HVDCP_NO_AUTH_QC3_CFG_BIT		BIT(1)
+
+#define USBIN_LOAD_CFG				0x365
+#define ICL_OVERRIDE_AFTER_APSD_BIT		BIT(4)
+#define USBIN_AICL_STEP_TIMING_SEL_MASK		GENMASK(3, 2)
+#define USBIN_IN_COLLAPSE_GF_SEL_MASK		GENMASK(1, 0)
+
+#define USBIN_ICL_OPTIONS			0x366
+#define CFG_USB3P0_SEL_BIT			BIT(2)
+#define USB51_MODE_BIT				BIT(1)
+#define USBIN_MODE_CHG_BIT			BIT(0)
+
+#define USBIN_CURRENT_LIMIT_CFG			0x370
+#define USBIN_CURRENT_LIMIT_MASK		GENMASK(7, 0)
+
+#define USBIN_AICL_OPTIONS_CFG			0x380
+#define SUSPEND_ON_COLLAPSE_USBIN_BIT		BIT(7)
+#define USBIN_AICL_PERIODIC_RERUN_EN_BIT	BIT(4)
+#define USBIN_AICL_ADC_EN_BIT			BIT(3)
+#define USBIN_AICL_EN_BIT			BIT(2)
+
+#define USBIN_5V_AICL_THRESHOLD_CFG		0x381
+#define USBIN_5V_AICL_THRESHOLD_CFG_MASK	GENMASK(2, 0)
+
+#define USBIN_CONT_AICL_THRESHOLD_CFG		0x384
+#define USBIN_CONT_AICL_THRESHOLD_CFG_MASK	GENMASK(5, 0)
+
+#define DCIN_CMD_IL				0x440
+#define DCIN_SUSPEND_BIT			BIT(0)
+
+#define TYPE_C_SNK_STATUS			0x506
+#define DETECTED_SRC_TYPE_MASK			GENMASK(6, 0)
+#define SNK_RP_STD_DAM_BIT			BIT(6)
+#define SNK_RP_1P5_DAM_BIT			BIT(5)
+#define SNK_RP_3P0_DAM_BIT			BIT(4)
+#define SNK_DAM_MASK				GENMASK(6, 4)
+#define SNK_DAM_500MA_BIT			BIT(6)
+#define SNK_DAM_1500MA_BIT			BIT(5)
+#define SNK_DAM_3000MA_BIT			BIT(4)
+#define SNK_RP_STD_BIT				BIT(3)
+#define SNK_RP_1P5_BIT				BIT(2)
+#define SNK_RP_3P0_BIT				BIT(1)
+#define SNK_RP_SHORT_BIT			BIT(0)
+
+#define TYPE_C_MODE_CFG				0x544
+#define TYPEC_TRY_MODE_MASK			GENMASK(4, 3)
+#define EN_TRY_SNK_BIT				BIT(4)
+#define EN_TRY_SRC_BIT				BIT(3)
+#define TYPEC_POWER_ROLE_CMD_MASK		GENMASK(2, 0)
+#define EN_SRC_ONLY_BIT				BIT(2)
+#define EN_SNK_ONLY_BIT				BIT(1)
+#define TYPEC_DISABLE_CMD_BIT			BIT(0)
+
+#define TYPEC_TYPE_C_VCONN_CONTROL		0x546
+#define VCONN_EN_ORIENTATION_BIT		BIT(2)
+#define VCONN_EN_VALUE_BIT			BIT(1)
+#define VCONN_EN_SRC_BIT			BIT(0)
+
+#define TYPE_C_DEBUG_ACCESS_SINK		0x54a
+#define TYPEC_DEBUG_ACCESS_SINK_MASK		GENMASK(4, 0)
+
+#define DEBUG_ACCESS_SRC_CFG			0x54C
+#define EN_UNORIENTED_DEBUG_ACCESS_SRC_BIT	BIT(0)
+
+#define TYPE_C_EXIT_STATE_CFG			0x550
+#define BYPASS_VSAFE0V_DURING_ROLE_SWAP_BIT	BIT(3)
+#define SEL_SRC_UPPER_REF_BIT			BIT(2)
+#define EXIT_SNK_BASED_ON_CC_BIT		BIT(0)
+
+#define TYPE_C_INTERRUPT_EN_CFG_1			0x55e
+#define TYPEC_LEGACY_CABLE_INT_EN_BIT			BIT(7)
+#define TYPEC_NONCOMPLIANT_LEGACY_CABLE_INT_EN_BIT	BIT(6)
+#define TYPEC_TRYSOURCE_DETECT_INT_EN_BIT		BIT(5)
+#define TYPEC_TRYSINK_DETECT_INT_EN_BIT			BIT(4)
+#define TYPEC_CCOUT_DETACH_INT_EN_BIT			BIT(3)
+#define TYPEC_CCOUT_ATTACH_INT_EN_BIT			BIT(2)
+#define TYPEC_VBUS_DEASSERT_INT_EN_BIT			BIT(1)
+#define TYPEC_VBUS_ASSERT_INT_EN_BIT			BIT(0)
+
+#define BARK_BITE_WDOG_PET			0x643
+#define BARK_BITE_WDOG_PET_BIT			BIT(0)
+
+#define WD_CFG					0x651
+#define WATCHDOG_TRIGGER_AFP_EN_BIT		BIT(7)
+#define BARK_WDOG_INT_EN_BIT			BIT(6)
+#define BITE_WDOG_INT_EN_BIT			BIT(5)
+#define SFT_AFTER_WDOG_IRQ_MASK			GENMASK(4, 3)
+#define WDOG_IRQ_SFT_BIT			BIT(2)
+#define WDOG_TIMER_EN_ON_PLUGIN_BIT		BIT(1)
+#define WDOG_TIMER_EN_BIT			BIT(0)
+
+#define SNARL_BARK_BITE_WD_CFG			0x653
+#define BITE_WDOG_DISABLE_CHARGING_CFG_BIT	BIT(7)
+#define SNARL_WDOG_TIMEOUT_MASK			GENMASK(6, 4)
+#define BARK_WDOG_TIMEOUT_MASK			GENMASK(3, 2)
+#define BITE_WDOG_TIMEOUT_MASK			GENMASK(1, 0)
+
+#define AICL_RERUN_TIME_CFG			0x661
+#define AICL_RERUN_TIME_MASK			GENMASK(1, 0)
+
+#define SDP_CURRENT_UA			500000
+#define CDP_CURRENT_UA			3000000
+#define DCP_CURRENT_UA			3300000
+#define CURRENT_MAX_UA			DCP_CURRENT_UA
+
+/* pmi8150b registers represent current in increments of 1/40th of an amp */
+#define CURRENT_SCALE_FACTOR		50000
+/* clang-format on */
+
+enum charger_status {
+	TRICKLE_CHARGE = 0,
+	PRE_CHARGE,
+	FAST_CHARGE,
+	FULLON_CHARGE,
+	TAPER_CHARGE,
+	TERMINATE_CHARGE,
+	INHIBIT_CHARGE,
+	DISABLE_CHARGE,
+};
+
+struct smb5_register {
+	u16 addr;
+	u8 mask;
+	u8 val;
+};
+
+/**
+ * struct smb5_chip - smb5 chip structure
+ * @dev:		Device reference for power_supply
+ * @name:		The platform device name
+ * @base:		Base address for smb5 registers
+ * @regmap:		Register map
+ * @batt_info:		Battery data from DT
+ * @status_change_work: Worker to handle plug/unplug events
+ * @cable_irq:		USB plugin IRQ
+ * @wakeup_enabled:	If the cable IRQ will cause a wakeup
+ * @usb_in_i_chan:	USB_IN current measurement channel
+ * @usb_in_v_chan:	USB_IN voltage measurement channel
+ * @chg_psy:		Charger power supply instance
+ */
+struct smb5_chip {
+	struct device *dev;
+	const char *name;
+	unsigned int base;
+	struct regmap *regmap;
+	struct power_supply_battery_info *batt_info;
+
+	struct delayed_work status_change_work;
+	int cable_irq;
+	bool wakeup_enabled;
+
+	struct iio_channel *usb_in_i_chan;
+	struct iio_channel *usb_in_v_chan;
+
+	struct power_supply *chg_psy;
+};
+
+static enum power_supply_property smb5_properties[] = {
+	POWER_SUPPLY_PROP_MANUFACTURER,
+	POWER_SUPPLY_PROP_MODEL_NAME,
+	POWER_SUPPLY_PROP_CURRENT_MAX,
+	POWER_SUPPLY_PROP_CURRENT_NOW,
+	POWER_SUPPLY_PROP_VOLTAGE_NOW,
+	POWER_SUPPLY_PROP_STATUS,
+	POWER_SUPPLY_PROP_HEALTH,
+	POWER_SUPPLY_PROP_ONLINE,
+	POWER_SUPPLY_PROP_USB_TYPE,
+	POWER_SUPPLY_PROP_CHARGING_ENABLED,
+};
+
+static int smb5_get_prop_usb_online(struct smb5_chip *chip, int *val)
+{
+	unsigned int stat;
+	int rc;
+
+	rc = regmap_read(chip->regmap, chip->base + USBIN_INT_RT_STS_OFFSET, &stat);
+	if (rc < 0) {
+		dev_err(chip->dev, "Couldn't read USBIN_RT_STS rc=%d\n", rc);
+		return rc;
+	}
+
+	*val = (stat & USBIN_PLUGIN_RT_STS_BIT) ? 1 : 0;
+	return 0;
+}
+
+/*
+ * Qualcomm "automatic power source detection" aka APSD
+ * tells us what type of charger we're connected to.
+ */
+static int smb5_apsd_get_charger_type(struct smb5_chip *chip, int *val)
+{
+	unsigned int apsd_stat, stat;
+	int usb_online = 0;
+	int rc;
+
+	rc = smb5_get_prop_usb_online(chip, &usb_online);
+	if (!usb_online) {
+		*val = POWER_SUPPLY_USB_TYPE_UNKNOWN;
+		return rc;
+	}
+
+	rc = regmap_read(chip->regmap, chip->base + APSD_STATUS, &apsd_stat);
+	if (rc < 0) {
+		dev_err(chip->dev, "Failed to read apsd status, rc = %d", rc);
+		return rc;
+	}
+	if (!(apsd_stat & APSD_DTC_STATUS_DONE_BIT)) {
+		dev_err(chip->dev, "Apsd not ready");
+		return -EAGAIN;
+	}
+
+	rc = regmap_read(chip->regmap, chip->base + APSD_RESULT_STATUS, &stat);
+	if (rc < 0) {
+		dev_err(chip->dev, "Failed to read apsd result, rc = %d", rc);
+		return rc;
+	}
+
+	stat &= APSD_RESULT_STATUS_MASK;
+
+	if (stat & CDP_CHARGER_BIT){
+		*val = POWER_SUPPLY_USB_TYPE_CDP;
+	} else if (stat & DCP_CHARGER_BIT){
+		*val = POWER_SUPPLY_USB_TYPE_DCP;
+	} else if (stat & OCP_CHARGER_BIT){
+		*val = POWER_SUPPLY_USB_TYPE_DCP;
+	} else if (stat & FLOAT_CHARGER_BIT){
+		*val = POWER_SUPPLY_USB_TYPE_DCP;
+	} else if (stat & QC_2P0_BIT){
+		*val = POWER_SUPPLY_USB_TYPE_DCP;
+	} else if (stat & QC_3P0_BIT){
+		*val = POWER_SUPPLY_USB_TYPE_DCP;
+	} else {
+		*val = POWER_SUPPLY_USB_TYPE_SDP;
+	}
+
+	return 0;
+}
+
+static int smb5_get_prop_charging_enabled(struct smb5_chip *chip, int *val)
+{
+	unsigned int charging_enabled;
+	int rc = regmap_read(chip->regmap, chip->base + CHARGING_ENABLE_CMD, &charging_enabled);
+	if (rc < 0) {
+		dev_err(chip->dev, "Failed to read charging enabled status, rc = %d", rc);
+		return rc;
+	}
+	*val = charging_enabled & CHARGING_ENABLE_CMD_BIT ? 1 : 0;
+	return 0;
+}
+
+static int smb5_get_prop_status(struct smb5_chip *chip, int *val)
+{
+	unsigned char stat[2];
+	int usb_online = 0;
+	int rc;
+
+	rc = smb5_get_prop_usb_online(chip, &usb_online);
+	if (!usb_online) {
+		*val = POWER_SUPPLY_STATUS_DISCHARGING;
+		return rc;
+	}
+
+	rc = regmap_bulk_read(chip->regmap,
+			      chip->base + BATTERY_CHARGER_STATUS_1, &stat, 2);
+	if (rc < 0) {
+		dev_err(chip->dev, "Failed to read charging status ret=%d\n",
+			rc);
+		return rc;
+	}
+
+	if (stat[1] & VBATT_GTET_INHIBIT_BIT) {
+		*val = POWER_SUPPLY_STATUS_NOT_CHARGING;
+		return 0;
+	}
+
+	stat[0] = stat[0] & BATTERY_CHARGER_STATUS_MASK;
+
+	switch (stat[0]) {
+	case TRICKLE_CHARGE:
+	case PRE_CHARGE:
+	case FAST_CHARGE:
+	case FULLON_CHARGE:
+	case TAPER_CHARGE:
+		*val = POWER_SUPPLY_STATUS_CHARGING;
+		return rc;
+	case DISABLE_CHARGE:
+		*val = POWER_SUPPLY_STATUS_NOT_CHARGING;
+		return rc;
+	case TERMINATE_CHARGE:
+	case INHIBIT_CHARGE:
+		*val = POWER_SUPPLY_STATUS_FULL;
+		return rc;
+	default:
+		*val = POWER_SUPPLY_STATUS_UNKNOWN;
+		return rc;
+	}
+}
+
+static inline int smb5_get_current_limit(struct smb5_chip *chip,
+					 unsigned int *val)
+{
+	int rc = regmap_read(chip->regmap, chip->base + AICL_STATUS, val);
+
+	if (rc >= 0)
+		*val *= CURRENT_SCALE_FACTOR;
+	return rc;
+}
+
+static int smb5_set_current_limit(struct smb5_chip *chip, unsigned int val)
+{
+	unsigned char val_raw;
+
+	if (val > 4950000) {
+		dev_err(chip->dev,
+			"Can't set current limit higher than 4950000uA");
+		return -EINVAL;
+	}
+	val_raw = val / CURRENT_SCALE_FACTOR;
+
+	return regmap_write(chip->regmap, chip->base + USBIN_CURRENT_LIMIT_CFG,
+		val_raw);
+}
+
+static int smb5_set_prop_charging_enabled(struct smb5_chip *chip, unsigned int val)
+{
+	return regmap_update_bits(chip->regmap, chip->base + CHARGING_ENABLE_CMD,
+					CHARGING_ENABLE_CMD_BIT, val ? CHARGING_ENABLE_CMD_BIT : 0);
+}
+
+static void smb5_status_change_work(struct work_struct *work)
+{
+	unsigned int charger_type, current_ua;
+	int usb_online = 0;
+	int count, rc;
+	struct smb5_chip *chip;
+
+	chip = container_of(work, struct smb5_chip, status_change_work.work);
+
+	smb5_get_prop_usb_online(chip, &usb_online);
+	if (!usb_online)
+		return;
+
+	for (count = 0; count < 3; count++) {
+		dev_dbg(chip->dev, "get charger type retry %d\n", count);
+		rc = smb5_apsd_get_charger_type(chip, &charger_type);
+		if (rc != -EAGAIN)
+			break;
+		msleep(100);
+	}
+
+	if (rc < 0 && rc != -EAGAIN) {
+		dev_err(chip->dev, "get charger type failed: %d\n", rc);
+		return;
+	}
+
+	if (rc < 0) {
+		rc = regmap_update_bits(chip->regmap, chip->base + CMD_APSD,
+					APSD_RERUN_BIT, APSD_RERUN_BIT);
+		schedule_delayed_work(&chip->status_change_work,
+				      msecs_to_jiffies(1000));
+		dev_dbg(chip->dev, "get charger type failed, rerun apsd\n");
+		return;
+	}
+
+	switch (charger_type) {
+	case POWER_SUPPLY_USB_TYPE_CDP:
+		current_ua = CDP_CURRENT_UA;
+		break;
+	case POWER_SUPPLY_USB_TYPE_DCP:
+		current_ua = DCP_CURRENT_UA;
+		break;
+	case POWER_SUPPLY_USB_TYPE_SDP:
+	default:
+		current_ua = SDP_CURRENT_UA;
+		break;
+	}
+
+	smb5_set_current_limit(chip, current_ua);
+	power_supply_changed(chip->chg_psy);
+}
+
+static int smb5_get_iio_chan(struct smb5_chip *chip, struct iio_channel *chan,
+			     int *val)
+{
+	int rc;
+	union power_supply_propval status;
+
+	rc = power_supply_get_property(chip->chg_psy, POWER_SUPPLY_PROP_STATUS,
+				       &status);
+	if (rc < 0 || status.intval != POWER_SUPPLY_STATUS_CHARGING) {
+		*val = 0;
+		return 0;
+	}
+
+	if (IS_ERR(chan)) {
+		dev_err(chip->dev, "Failed to chan, err = %li", PTR_ERR(chan));
+		return PTR_ERR(chan);
+	}
+
+	return iio_read_channel_processed(chan, val);
+}
+
+static int smb5_get_prop_health(struct smb5_chip *chip, int *val)
+{
+	int rc;
+	unsigned int stat;
+
+	rc = regmap_read(chip->regmap, chip->base + BATTERY_CHARGER_STATUS_2,
+			 &stat);
+	if (rc < 0) {
+		dev_err(chip->dev, "Couldn't read charger status rc=%d\n", rc);
+		return rc;
+	}
+
+	if (stat & CHARGER_ERROR_STATUS_BAT_OV_BIT) {
+		dev_err(chip->dev, "battery over-voltage");
+	}
+
+	rc = regmap_read(chip->regmap, chip->base + BATTERY_CHARGER_STATUS_7_REG,
+			 &stat);
+	if (rc < 0) {
+		dev_err(chip->dev, "Couldn't read charger status 7 rc=%d\n", rc);
+		return rc;
+	}
+
+	if (stat & BAT_TEMP_STATUS_TOO_COLD_BIT)
+		*val = POWER_SUPPLY_HEALTH_COLD;
+	else if (stat & BAT_TEMP_STATUS_TOO_HOT_BIT)
+		*val = POWER_SUPPLY_HEALTH_OVERHEAT;
+	else if (stat & BAT_TEMP_STATUS_COLD_SOFT_BIT)
+		*val = POWER_SUPPLY_HEALTH_COOL;
+	else if (stat & BAT_TEMP_STATUS_HOT_SOFT_BIT)
+		*val = POWER_SUPPLY_HEALTH_WARM;
+	else
+		*val = POWER_SUPPLY_HEALTH_GOOD;
+
+	return 0;
+}
+
+static int smb5_get_property(struct power_supply *psy,
+			     enum power_supply_property psp,
+			     union power_supply_propval *val)
+{
+	struct smb5_chip *chip = power_supply_get_drvdata(psy);
+
+	switch (psp) {
+	case POWER_SUPPLY_PROP_MANUFACTURER:
+		val->strval = "Qualcomm";
+		return 0;
+	case POWER_SUPPLY_PROP_MODEL_NAME:
+		val->strval = chip->name;
+		return 0;
+	case POWER_SUPPLY_PROP_CURRENT_MAX:
+		return smb5_get_current_limit(chip, &val->intval);
+	case POWER_SUPPLY_PROP_CURRENT_NOW:
+		return smb5_get_iio_chan(chip, chip->usb_in_i_chan,
+					 &val->intval);
+	case POWER_SUPPLY_PROP_VOLTAGE_NOW:
+		return smb5_get_iio_chan(chip, chip->usb_in_v_chan,
+					 &val->intval);
+	case POWER_SUPPLY_PROP_ONLINE:
+		return smb5_get_prop_usb_online(chip, &val->intval);
+	case POWER_SUPPLY_PROP_STATUS:
+		return smb5_get_prop_status(chip, &val->intval);
+	case POWER_SUPPLY_PROP_HEALTH:
+		return smb5_get_prop_health(chip, &val->intval);
+	case POWER_SUPPLY_PROP_USB_TYPE:
+		return smb5_apsd_get_charger_type(chip, &val->intval);
+	case POWER_SUPPLY_PROP_CHARGING_ENABLED:
+		return smb5_get_prop_charging_enabled(chip, &val->intval);
+	default:
+		dev_err(chip->dev, "invalid property: %d\n", psp);
+		return -EINVAL;
+	}
+}
+
+static int smb5_set_property(struct power_supply *psy,
+			     enum power_supply_property psp,
+			     const union power_supply_propval *val)
+{
+	struct smb5_chip *chip = power_supply_get_drvdata(psy);
+
+	switch (psp) {
+	case POWER_SUPPLY_PROP_CURRENT_MAX:
+		return smb5_set_current_limit(chip, val->intval);
+	case POWER_SUPPLY_PROP_CHARGING_ENABLED:
+		return smb5_set_prop_charging_enabled(chip, val->intval);
+	default:
+		dev_err(chip->dev, "No setter for property: %d\n", psp);
+		return -EINVAL;
+	}
+}
+
+static int smb5_property_is_writable(struct power_supply *psy,
+				     enum power_supply_property psp)
+{
+	switch (psp) {
+	case POWER_SUPPLY_PROP_CURRENT_MAX:
+	case POWER_SUPPLY_PROP_CHARGING_ENABLED:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
+static irqreturn_t smb5_handle_batt_overvoltage(int irq, void *data)
+{
+	struct smb5_chip *chip = data;
+	unsigned int status;
+
+	regmap_read(chip->regmap, chip->base + BATTERY_CHARGER_STATUS_2,
+		    &status);
+
+	if (status & CHARGER_ERROR_STATUS_BAT_OV_BIT) {
+		/* The hardware stops charging automatically */
+		dev_err(chip->dev, "battery overvoltage detected\n");
+		power_supply_changed(chip->chg_psy);
+	}
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t smb5_handle_usb_plugin(int irq, void *data)
+{
+	struct smb5_chip *chip = data;
+
+	power_supply_changed(chip->chg_psy);
+
+	schedule_delayed_work(&chip->status_change_work,
+			      msecs_to_jiffies(1500));
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t smb5_handle_usb_icl_change(int irq, void *data)
+{
+	struct smb5_chip *chip = data;
+
+	power_supply_changed(chip->chg_psy);
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t smb5_handle_wdog_bark(int irq, void *data)
+{
+	struct smb5_chip *chip = data;
+	int rc;
+
+	power_supply_changed(chip->chg_psy);
+
+	rc = regmap_write(chip->regmap, BARK_BITE_WDOG_PET,
+			  BARK_BITE_WDOG_PET_BIT);
+	if (rc < 0)
+		dev_err(chip->dev, "Couldn't pet the dog rc=%d\n", rc);
+
+	return IRQ_HANDLED;
+}
+
+static const struct power_supply_desc smb5_psy_desc = {
+	.name = "pm8150b_charger",
+	.type = POWER_SUPPLY_TYPE_USB,
+	.usb_types = BIT(POWER_SUPPLY_USB_TYPE_SDP) |
+		     BIT(POWER_SUPPLY_USB_TYPE_CDP) |
+		     BIT(POWER_SUPPLY_USB_TYPE_DCP) |
+		     BIT(POWER_SUPPLY_USB_TYPE_UNKNOWN),
+	.properties = smb5_properties,
+	.num_properties = ARRAY_SIZE(smb5_properties),
+	.get_property = smb5_get_property,
+	.set_property = smb5_set_property,
+	.property_is_writeable = smb5_property_is_writable,
+};
+
+/* Init sequence derived from vendor downstream driver */
+static const struct smb5_register smb5_init_seq[] = {
+	{ .addr = USBIN_CMD_IL, .mask = USBIN_SUSPEND_BIT, .val = 0 },
+	{ .addr = AICL_RERUN_TIME_CFG, .mask = AICL_RERUN_TIME_MASK, .val = 0 },
+	/*
+	 * By default configure us as an upstream facing port
+	 * FIXME: This will be handled by the type-c driver
+	 */
+	{ .addr = TYPE_C_MODE_CFG,
+	  .mask = EN_TRY_SNK_BIT | EN_SNK_ONLY_BIT,
+	  .val = EN_TRY_SNK_BIT },
+	{ .addr = TYPEC_TYPE_C_VCONN_CONTROL,
+	  .mask = VCONN_EN_ORIENTATION_BIT | VCONN_EN_SRC_BIT |
+		  VCONN_EN_VALUE_BIT,
+	  .val = VCONN_EN_SRC_BIT },
+	{ .addr = DEBUG_ACCESS_SRC_CFG,
+	  .mask = EN_UNORIENTED_DEBUG_ACCESS_SRC_BIT,
+	  .val = EN_UNORIENTED_DEBUG_ACCESS_SRC_BIT },
+	{ .addr = TYPE_C_EXIT_STATE_CFG,
+	  .mask = SEL_SRC_UPPER_REF_BIT,
+	  .val = SEL_SRC_UPPER_REF_BIT },
+	/*
+	 * Disable Type-C factory mode and stay in Attached.SRC state when VCONN
+	 * over-current happens
+	 */
+	{ .addr = TYPE_C_CFG,
+	  .mask = BC1P2_START_ON_CC_BIT,
+	  .val = 0 },
+	{ .addr = TYPE_C_DEBUG_ACCESS_SINK,
+	  .mask = TYPEC_DEBUG_ACCESS_SINK_MASK,
+	  .val = 0x17 },
+	/* Configure VBUS for software control */
+	{ .addr = OTG_CFG, .mask = OTG_EN_SRC_CFG_BIT, .val = 0 },
+	/*
+	 * Use VBAT to determine the recharge threshold when battery is full
+	 * rather than the state of charge.
+	 */
+	{ .addr = CHARGE_RCHG_SOC_THRESHOLD_CFG_REG,
+	  .mask = CHARGE_RCHG_SOC_THRESHOLD_CFG_MASK,
+	  .val = 98 },
+	/* Enable charging */
+	{ .addr = CHARGING_ENABLE_CMD,
+	  .mask = CHARGING_ENABLE_CMD_BIT,
+	  .val = CHARGING_ENABLE_CMD_BIT },
+	/* Enable BC1P2 Src detect */
+	{ .addr = USBIN_OPTIONS_1_CFG,
+	  .mask = BC1P2_SRC_DETECT_BIT,
+	  .val = BC1P2_SRC_DETECT_BIT },
+	/* Set the default SDP charger type to a 500ma USB 2.0 port */
+	{ .addr = USBIN_ICL_OPTIONS,
+	  .mask = USBIN_MODE_CHG_BIT,
+	  .val = USBIN_MODE_CHG_BIT },
+	{ .addr = CMD_ICL_OVERRIDE,
+	  .mask = ICL_OVERRIDE_BIT,
+	  .val = 0 },
+	{ .addr = USBIN_LOAD_CFG,
+	  .mask = ICL_OVERRIDE_AFTER_APSD_BIT,
+	  .val = 0 },
+	/* Disable watchdog */
+	{ .addr = SNARL_BARK_BITE_WD_CFG, .mask = 0xff, .val = 0 },
+	{ .addr = WD_CFG,
+	  .mask = WATCHDOG_TRIGGER_AFP_EN_BIT | WDOG_TIMER_EN_ON_PLUGIN_BIT |
+		  BARK_WDOG_INT_EN_BIT,
+	  .val = 0 },
+	/*
+	 * Enable Automatic Input Current Limit, this will slowly ramp up the current
+	 * When connected to a wall charger, and automatically stop when it detects
+	 * the charger current limit (voltage drop?) or it reaches the programmed limit.
+	 */
+	{ .addr = USBIN_AICL_OPTIONS_CFG,
+	  .mask = USBIN_AICL_PERIODIC_RERUN_EN_BIT | USBIN_AICL_ADC_EN_BIT
+			| USBIN_AICL_EN_BIT | SUSPEND_ON_COLLAPSE_USBIN_BIT,
+	  .val = USBIN_AICL_PERIODIC_RERUN_EN_BIT | USBIN_AICL_ADC_EN_BIT
+			| USBIN_AICL_EN_BIT | SUSPEND_ON_COLLAPSE_USBIN_BIT },
+};
+
+static int smb5_init_hw(struct smb5_chip *chip)
+{
+	int rc, i;
+	for (i = 0; i < ARRAY_SIZE(smb5_init_seq); i++) {
+		dev_dbg(chip->dev, "%d: Writing 0x%02x to 0x%02x\n", i,
+			smb5_init_seq[i].val, smb5_init_seq[i].addr);
+		rc = regmap_update_bits(chip->regmap,
+					chip->base + smb5_init_seq[i].addr,
+					smb5_init_seq[i].mask,
+					smb5_init_seq[i].val);
+		if (rc < 0)
+			return dev_err_probe(chip->dev, rc,
+					     "%s: init command %d failed\n",
+					     __func__, i);
+	}
+	return 0;
+}
+
+static int smb5_init_irq(struct smb5_chip *chip, int *irq, const char *name,
+			 irqreturn_t (*handler)(int irq, void *data))
+{
+	int irqnum;
+	int rc;
+
+	irqnum = platform_get_irq_byname(to_platform_device(chip->dev), name);
+	if (irqnum < 0)
+		return irqnum;
+
+	rc = devm_request_threaded_irq(chip->dev, irqnum, NULL, handler,
+				       IRQF_ONESHOT, name, chip);
+	if (rc < 0)
+		return dev_err_probe(chip->dev, rc, "Couldn't request irq %s\n",
+				     name);
+
+	if (irq)
+		*irq = irqnum;
+
+	return 0;
+}
+
+static int smb5_probe(struct platform_device *pdev)
+{
+	struct power_supply_config supply_config = {};
+	struct power_supply_desc *desc;
+	struct smb5_chip *chip;
+	int rc, irq;
+
+	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
+	if (!chip)
+		return -ENOMEM;
+
+	chip->dev = &pdev->dev;
+	chip->name = pdev->name;
+
+	chip->regmap = dev_get_regmap(pdev->dev.parent, NULL);
+	if (!chip->regmap)
+		return dev_err_probe(chip->dev, -ENODEV,
+				     "failed to locate the regmap\n");
+
+	rc = device_property_read_u32(chip->dev, "reg", &chip->base);
+	if (rc < 0)
+		return dev_err_probe(chip->dev, rc,
+				     "Couldn't read base address\n");
+
+	chip->usb_in_v_chan = devm_iio_channel_get(chip->dev, "usb_in_v_div_16");
+	if (IS_ERR(chip->usb_in_v_chan))
+		return dev_err_probe(chip->dev, PTR_ERR(chip->usb_in_v_chan),
+				     "Couldn't get usb_in_v_div_16 IIO channel\n");
+
+	chip->usb_in_i_chan = devm_iio_channel_get(chip->dev, "usb_in_i_uv");
+	if (IS_ERR(chip->usb_in_i_chan)) {
+		return dev_err_probe(chip->dev, PTR_ERR(chip->usb_in_i_chan),
+				     "Couldn't get usb_in_i_uv IIO channel\n");
+	}
+
+	rc = smb5_init_hw(chip);
+	if (rc < 0)
+		return rc;
+
+	supply_config.drv_data = chip;
+	supply_config.fwnode = pdev->dev.fwnode;
+
+	desc = devm_kzalloc(chip->dev, sizeof(smb5_psy_desc), GFP_KERNEL);
+	if (!desc)
+		return -ENOMEM;
+	memcpy(desc, &smb5_psy_desc, sizeof(smb5_psy_desc));
+	desc->name =
+		devm_kasprintf(chip->dev, GFP_KERNEL, "%s-charger",
+			       (const char *)device_get_match_data(chip->dev));
+	if (!desc->name)
+		return -ENOMEM;
+
+	chip->chg_psy =
+		devm_power_supply_register(chip->dev, desc, &supply_config);
+	if (IS_ERR(chip->chg_psy))
+		return dev_err_probe(chip->dev, PTR_ERR(chip->chg_psy),
+				     "failed to register power supply\n");
+
+	rc = power_supply_get_battery_info(chip->chg_psy, &chip->batt_info);
+	if (rc)
+		return dev_err_probe(chip->dev, rc,
+				     "Failed to get battery info\n");
+
+	rc = devm_delayed_work_autocancel(chip->dev, &chip->status_change_work,
+					  smb5_status_change_work);
+	if (rc)
+		return dev_err_probe(chip->dev, rc,
+				     "Failed to init status change work\n");
+
+	rc = (chip->batt_info->voltage_max_design_uv - 3487500) / 7500 + 1;
+	rc = regmap_update_bits(chip->regmap, chip->base + FLOAT_VOLTAGE_CFG,
+				FLOAT_VOLTAGE_SETTING_MASK, rc);
+	if (rc < 0)
+		return dev_err_probe(chip->dev, rc, "Couldn't set vbat max\n");
+
+	rc = smb5_init_irq(chip, &irq, "bat-ov", smb5_handle_batt_overvoltage);
+	if (rc < 0)
+		return rc;
+
+	rc = smb5_init_irq(chip, &chip->cable_irq, "usbin-plugin",
+			   smb5_handle_usb_plugin);
+	if (rc < 0)
+		return rc;
+
+	rc = smb5_init_irq(chip, &irq, "usbin-icl-change",
+			   smb5_handle_usb_icl_change);
+	if (rc < 0)
+		return rc;
+	rc = smb5_init_irq(chip, &irq, "wdog-bark", smb5_handle_wdog_bark);
+	if (rc < 0)
+		return rc;
+
+	rc = dev_pm_set_wake_irq(chip->dev, chip->cable_irq);
+	if (rc < 0)
+		return dev_err_probe(chip->dev, rc, "Couldn't set wake irq\n");
+
+	platform_set_drvdata(pdev, chip);
+
+	/* Initialise charger state */
+	schedule_delayed_work(&chip->status_change_work, 0);
+
+	return 0;
+}
+
+static const struct of_device_id smb5_match_id_table[] = {
+	{ .compatible = "qcom,pm8150b-charger", .data = "pm8150b" },
+	{ /* sentinal */ }
+};
+MODULE_DEVICE_TABLE(of, smb5_match_id_table);
+
+static struct platform_driver qcom_spmi_smb5 = {
+	.probe = smb5_probe,
+	.driver = {
+		.name = "qcom-pm8150b-charger",
+		.of_match_table = smb5_match_id_table,
+		},
+};
+
+module_platform_driver(qcom_spmi_smb5);
+
+MODULE_AUTHOR("Caleb Connolly <caleb.connolly@linaro.org>");
+MODULE_DESCRIPTION("Qualcomm SMB5 Charger Driver");
+MODULE_LICENSE("GPL");
diff --git a/include/linux/power_supply.h b/include/linux/power_supply.h
index 360ffdf272da..258e5f06659d 100644
--- a/include/linux/power_supply.h
+++ b/include/linux/power_supply.h
@@ -178,6 +178,7 @@ enum power_supply_property {
 	POWER_SUPPLY_PROP_MANUFACTURE_DAY,
 	POWER_SUPPLY_PROP_INTERNAL_RESISTANCE,
 	POWER_SUPPLY_PROP_STATE_OF_HEALTH,
+	POWER_SUPPLY_PROP_CHARGING_ENABLED,
 	/* Properties of type `const char *' */
 	POWER_SUPPLY_PROP_MODEL_NAME,
 	POWER_SUPPLY_PROP_MANUFACTURER,
-- 
2.52.0
