From e3c63efd4637a9f00d21d45514442a9f5ece0f40 Mon Sep 17 00:00:00 2001
From: ayakael <antoine@ayakael.net>
Date: Sun, 8 Feb 2026 09:35:35 -0500
Subject: [PATCH 1/5] drm: panel: add clockwork cwu50

---
 drivers/gpu/drm/panel/Kconfig           |  33 +
 drivers/gpu/drm/panel/Makefile          |   3 +
 drivers/gpu/drm/panel/panel-cwd686.c    | 296 +++++++++
 drivers/gpu/drm/panel/panel-cwu50-cm3.c | 598 +++++++++++++++++
 drivers/gpu/drm/panel/panel-cwu50.c     | 846 ++++++++++++++++++++++++
 5 files changed, 1776 insertions(+)
 create mode 100644 drivers/gpu/drm/panel/panel-cwd686.c
 create mode 100644 drivers/gpu/drm/panel/panel-cwu50-cm3.c
 create mode 100644 drivers/gpu/drm/panel/panel-cwu50.c

diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 928b9f1bf7d5..1a750ba2af1e 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -96,6 +96,39 @@ config DRM_PANEL_BOE_TV101WUM_LL2
 	  Say Y here if you want to support for BOE TV101WUM-LL2
 	  WUXGA PANEL DSI Video Mode panel
 
+config DRM_PANEL_CWD686
+	tristate "CWD686 panel"
+ 	depends on OF
+	depends on DRM_MIPI_DSI
+	depends on BACKLIGHT_CLASS_DEVICE
+	help
+	  Say Y here if you want to enable support for CWD686 panel.
+	  The panel has a 480x1280 resolution and uses 24 bit RGB per pixel.
+	  To compile this driver as a module, choose M here: the module
+	  will be called panel-cwd686.
+
+config DRM_PANEL_CWU50
+	tristate "CWU50 panel"
+ 	depends on OF
+	depends on DRM_MIPI_DSI
+	depends on BACKLIGHT_CLASS_DEVICE
+	help
+	  Say Y here if you want to enable support for CWU50 panel.
+	  The panel has a 720x1280 resolution and uses 24 bit RGB per pixel.
+	  To compile this driver as a module, choose M here: the module
+	  will be called panel-cwu50.
+
+config DRM_PANEL_CWU50_CM3
+	tristate "CWU50_CM3 panel"
+ 	depends on OF
+	depends on DRM_MIPI_DSI
+	depends on BACKLIGHT_CLASS_DEVICE
+	help
+	  Say Y here if you want to enable support for CWU50_CM3 panel.
+	  The panel has a 720x1280 resolution and uses 24 bit RGB per pixel.
+	  To compile this driver as a module, choose M here: the module
+	  will be called panel-cwu50-cm3.
+
 config DRM_PANEL_EBBG_FT8719
 	tristate "EBBG FT8719 panel driver"
 	depends on OF
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index c13a08111d0c..7b89f14c5785 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -104,3 +104,6 @@ obj-$(CONFIG_DRM_PANEL_WAVESHARE_TOUCHSCREEN) += panel-waveshare-dsi.o
 obj-$(CONFIG_DRM_PANEL_WAVESHARE_TOUCHSCREEN_V2) += panel-waveshare-dsi-v2.o
 obj-$(CONFIG_DRM_PANEL_WIDECHIPS_WS2401) += panel-widechips-ws2401.o
 obj-$(CONFIG_DRM_PANEL_XINPENG_XPP055C272) += panel-xinpeng-xpp055c272.o
+obj-$(CONFIG_DRM_PANEL_CWD686) += panel-cwd686.o
+obj-$(CONFIG_DRM_PANEL_CWU50) += panel-cwu50.o
+obj-$(CONFIG_DRM_PANEL_CWU50) += panel-cwu50-cm3.o
diff --git a/drivers/gpu/drm/panel/panel-cwd686.c b/drivers/gpu/drm/panel/panel-cwd686.c
new file mode 100644
index 000000000000..e429e8ddf969
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-cwd686.c
@@ -0,0 +1,296 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <drm/drm_modes.h>
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_panel.h>
+#include <linux/backlight.h>
+#include <linux/gpio/consumer.h>
+#include <linux/regulator/consumer.h>
+#include <linux/delay.h>
+#include <linux/of_device.h>
+#include <linux/module.h>
+
+struct cwd686 {
+	struct device *dev;
+	struct drm_panel panel;
+	struct regulator *supply;
+	struct gpio_desc *reset_gpio;
+	struct backlight_device *backlight;
+	bool prepared;
+	bool enabled;
+	enum drm_panel_orientation orientation;
+};
+
+static const struct drm_display_mode default_mode = {
+	.clock = 54465,
+	.hdisplay = 480,
+	.hsync_start = 480 + 150,
+	.hsync_end = 480 + 150 + 24,
+	.htotal = 480 + 150 + 24 + 40,
+	.vdisplay = 1280,
+	.vsync_start = 1280 + 12,
+	.vsync_end = 1280 + 12+ 6,
+	.vtotal = 1280 + 12 + 6 + 10,
+};
+
+static inline struct cwd686 *panel_to_cwd686(struct drm_panel *panel)
+{
+	return container_of(panel, struct cwd686, panel);
+}
+
+#define dcs_write_seq(seq...)                              \
+({                                                              \
+	static const u8 d[] = { seq };                          \
+	mipi_dsi_dcs_write_buffer(dsi, d, ARRAY_SIZE(d));	 \
+})
+
+static void cwd686_init_sequence(struct cwd686 *ctx) 
+{
+	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+
+	dcs_write_seq(0xF0,0x5A,0x59);
+	dcs_write_seq(0xF1,0xA5,0xA6);
+	dcs_write_seq(0xB0,0x54,0x32,0x23,0x45,0x44,0x44,0x44,0x44,0x9F,0x00,0x01,0x9F,0x00,0x01);
+	dcs_write_seq(0xB1,0x32,0x84,0x02,0x83,0x29,0x06,0x06,0x72,0x06,0x06);
+	dcs_write_seq(0xB2,0x73);
+	dcs_write_seq(0xB3,0x0B,0x09,0x13,0x11,0x0F,0x0D,0x00,0x00,0x00,0x03,0x00,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x05,0x07);
+	dcs_write_seq(0xB4,0x0A,0x08,0x12,0x10,0x0E,0x0C,0x00,0x00,0x00,0x03,0x00,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x04,0x06);
+	dcs_write_seq(0xB6,0x13,0x13);
+	dcs_write_seq(0xB8,0xB4,0x43,0x02,0xCC);
+	dcs_write_seq(0xB9,0xA5,0x20,0xFF,0xC8);
+	dcs_write_seq(0xBA,0x88,0x23);
+	dcs_write_seq(0xBD,0x43,0x0E,0x0E,0x50,0x50,0x29,0x10,0x03,0x44,0x03);
+	dcs_write_seq(0xC1,0x00,0x0C,0x16,0x04,0x00,0x30,0x10,0x04);
+	dcs_write_seq(0xC2,0x21,0x81);
+	dcs_write_seq(0xC3,0x02,0x30);
+	dcs_write_seq(0xC7,0x25,0x6A);
+	dcs_write_seq(0xC8,0x7C,0x68,0x59,0x4E,0x4B,0x3C,0x41,0x2B,0x44,0x43,0x43,0x60,0x4E,0x55,0x47,0x44,0x38,0x27,0x06,0x7C,0x68,0x59,0x4E,0x4B,0x3C,0x41,0x2B,0x44,0x43,0x43,0x60,0x4E,0x55,0x47,0x44,0x38,0x27,0x06);//GAMMA2.2
+	//dcs_write_seq(0xC8,0x7C,0x66,0x56,0x4A,0x46,0x37,0x3B,0x24,0x3D,0x3C,0x3A,0x56,0x42,0x48,0x39,0x38,0x2C,0x17,0x06,0x7C,0x66,0x56,0x4A,0x46,0x37,0x3B,0x24,0x3D,0x3C,0x3A,0x56,0x42,0x48,0x39,0x38,0x2C,0x17,0x06);//GAMMA2.5
+	//dcs_write_seq(0xC8,0x7C,0x69,0x5B,0x50,0x4E,0x40,0x46,0x31,0x4A,0x49,0x49,0x67,0x56,0x5E,0x51,0x4E,0x41,0x2F,0x06,0x7C,0x69,0x5B,0x50,0x4E,0x40,0x46,0x31,0x4A,0x49,0x49,0x67,0x56,0x5E,0x51,0x4E,0x41,0x2F,0x06);//GAMMA2.0
+	//dcs_write_seq(0xC8,0x7C,0x6D,0x60,0x56,0x54,0x47,0x4c,0x37,0x50,0x4e,0x4e,0x6d,0x5c,0x66,0x59,0x56,0x4A,0x36,0x06,0x7C,0x6D,0x60,0x56,0x54,0x47,0x4c,0x37,0x50,0x4e,0x4e,0x6d,0x5c,0x66,0x59,0x56,0x4A,0x36,0x06);//GAMMA1.8
+	//dcs_write_seq(0xC8,0x7C,0x6e,0x62,0x59,0x58,0x4b,0x52,0x3d,0x57,0x56,0x56,0x75,0x66,0x71,0x66,0x64,0x55,0x44,0x06,0x7C,0x6e,0x62,0x59,0x58,0x4b,0x52,0x3d,0x57,0x56,0x56,0x75,0x66,0x71,0x66,0x64,0x55,0x44,0x06);//GAMMA1.6
+	dcs_write_seq(0xD4,0x00,0x00,0x00,0x32,0x04,0x51);
+	dcs_write_seq(0xF1,0x5A,0x59);
+	dcs_write_seq(0xF0,0xA5,0xA6);
+	dcs_write_seq(0x36,0x14);
+	dcs_write_seq(0x35,0x00);
+	dcs_write_seq(0x11);
+	msleep(120);
+	dcs_write_seq(0x29);
+	msleep(20);
+}
+
+static int cwd686_disable(struct drm_panel *panel)
+{
+	struct cwd686 *ctx = panel_to_cwd686(panel);
+
+	if (!ctx->enabled)
+		return 0;
+
+	backlight_disable(ctx->backlight);
+
+	ctx->enabled = false;
+
+	return 0;
+}
+
+static int cwd686_unprepare(struct drm_panel *panel)
+{
+#if 0
+	struct cwd686 *ctx = panel_to_cwd686(panel);
+	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+	int ret;
+
+	if (!ctx->prepared)
+		return 0;
+
+	ret = mipi_dsi_dcs_set_display_off(dsi);
+	if (ret) {
+		dev_err(ctx->dev, "failed to turn display off (%d)\n", ret);
+		return ret;
+	}
+
+	ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
+	if (ret) {
+		dev_err(ctx->dev, "failed to enter sleep mode (%d)\n", ret);
+		return ret;
+	}
+	msleep(120);
+
+	gpiod_set_value_cansleep(ctx->reset_gpio, 0);
+	msleep(5);
+
+	ctx->prepared = false;
+#endif
+
+	return 0;
+}
+
+static int cwd686_prepare(struct drm_panel *panel)
+{
+	struct cwd686 *ctx = panel_to_cwd686(panel);
+	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+	int ret;
+
+	if (ctx->prepared)
+		return 0;
+
+	gpiod_set_value_cansleep(ctx->reset_gpio, 0);
+	msleep(10);
+	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+	msleep(120);
+
+	/* Enabe tearing mode: send TE (tearing effect) at VBLANK */
+	ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
+	if (ret) {
+		dev_err(ctx->dev, "failed to enable vblank TE (%d)\n", ret);
+		return ret;
+	}
+	/* Exit sleep mode and power on */
+
+	cwd686_init_sequence(ctx);
+
+	ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
+	if (ret) {
+		dev_err(ctx->dev, "failed to exit sleep mode (%d)\n", ret);
+		return ret;
+	}
+	msleep(120);
+
+	ret = mipi_dsi_dcs_set_display_on(dsi);
+	if (ret) {
+		dev_err(ctx->dev, "failed to turn display on (%d)\n", ret);
+		return ret;
+	}
+	msleep(20);
+
+	ctx->prepared = true;
+
+	return 0;
+}
+
+static int cwd686_enable(struct drm_panel *panel)
+{
+	struct cwd686 *ctx = panel_to_cwd686(panel);
+
+	if (ctx->enabled)
+		return 0;
+
+	backlight_enable(ctx->backlight);
+
+	ctx->enabled = true;
+
+	return 0;
+}
+
+static int cwd686_get_modes(struct drm_panel *panel, struct drm_connector *connector)
+{
+	struct cwd686 *ctx = panel_to_cwd686(panel);
+	struct drm_display_mode *mode;
+
+	mode = drm_mode_duplicate(connector->dev, &default_mode);
+	if (!mode) {
+		dev_err(panel->dev, "bad mode or failed to add mode\n");
+		return -EINVAL;
+	}
+	drm_mode_set_name(mode);
+	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
+
+	connector->display_info.width_mm = mode->width_mm;
+	connector->display_info.height_mm = mode->height_mm;
+
+	/* set up connector's "panel orientation" property */
+	drm_connector_set_panel_orientation(connector, ctx->orientation);
+
+	drm_mode_probed_add(connector, mode);
+
+	return 1; /* Number of modes */
+}
+
+static const struct drm_panel_funcs cwd686_drm_funcs = {
+	.disable = cwd686_disable,
+	.unprepare = cwd686_unprepare,
+	.prepare = cwd686_prepare,
+	.enable = cwd686_enable,
+	.get_modes = cwd686_get_modes,
+};
+
+static int cwd686_probe(struct mipi_dsi_device *dsi)
+{
+	struct device *dev = &dsi->dev;
+	struct cwd686 *ctx;
+	int ret;
+
+	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
+	if (!ctx)
+		return -ENOMEM;
+
+	mipi_dsi_set_drvdata(dsi, ctx);
+	ctx->dev = dev;
+
+	dsi->lanes = 4;
+	dsi->format = MIPI_DSI_FMT_RGB888;
+	dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | MIPI_DSI_MODE_LPM;
+
+	ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
+	if (IS_ERR(ctx->reset_gpio)) {
+		ret = PTR_ERR(ctx->reset_gpio);
+		if (ret != -EPROBE_DEFER)
+			dev_err(dev, "failed to request GPIO (%d)\n", ret);
+		return ret;
+	}
+
+	ctx->backlight = devm_of_find_backlight(dev);
+	if (IS_ERR(ctx->backlight)) {
+		dev_err(ctx->dev, "devm_of_find_backlight");
+		return PTR_ERR(ctx->backlight);
+	}
+
+	ret = of_drm_get_panel_orientation(dev->of_node, &ctx->orientation);
+	if (ret) {
+		dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, ret);
+		return ret;
+	}
+
+	ctx->panel.prepare_prev_first = true;
+
+	drm_panel_init(&ctx->panel, dev, &cwd686_drm_funcs, DRM_MODE_CONNECTOR_DSI);
+
+	drm_panel_add(&ctx->panel);
+
+	ret = mipi_dsi_attach(dsi);
+	if (ret < 0) {
+		dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret);
+		drm_panel_remove(&ctx->panel);
+		return ret;
+	}
+
+	return 0;
+}
+
+static void cwd686_remove(struct mipi_dsi_device *dsi)
+{
+	struct cwd686 *ctx = mipi_dsi_get_drvdata(dsi);
+
+	mipi_dsi_detach(dsi);
+	drm_panel_remove(&ctx->panel);
+}
+
+static const struct of_device_id cwd686_of_match[] = {
+	{ .compatible = "cw,cwd686" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, cwd686_of_match);
+
+static struct mipi_dsi_driver cwd686_driver = {
+	.probe = cwd686_probe,
+	.remove = cwd686_remove,
+	.driver = {
+		.name = "panel-cwd686",
+		.of_match_table = cwd686_of_match,
+	},
+};
+module_mipi_dsi_driver(cwd686_driver);
+
+MODULE_DESCRIPTION("DRM Driver for cwd686 MIPI DSI panel");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/panel/panel-cwu50-cm3.c b/drivers/gpu/drm/panel/panel-cwu50-cm3.c
new file mode 100644
index 000000000000..5a8eaf83c97a
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-cwu50-cm3.c
@@ -0,0 +1,598 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ * Copyright (c) 2021 Clockwork Tech LLC
+ * Copyright (c) 2021 Max Fierke <max@maxfierke.com>
+ *
+ */
+
+#include <drm/drm_modes.h>
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_panel.h>
+#include <linux/backlight.h>
+#include <linux/gpio/consumer.h>
+#include <linux/regulator/consumer.h>
+#include <linux/delay.h>
+#include <linux/of_device.h>
+#include <linux/module.h>
+#include <video/mipi_display.h>
+
+static int power_off_case = 1;
+module_param(power_off_case,int,0660);
+
+struct cwu50 {
+	struct device *dev;
+	struct drm_panel panel;
+	struct regulator *vci;
+	struct regulator *iovcc;
+	struct gpio_desc *reset_gpio;
+	enum drm_panel_orientation orientation;
+	int dsi_status; // 0: ok, 1: error
+	bool sysfs_node_created;
+};
+
+static ssize_t dsi_state_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct mipi_dsi_device *dsi = to_mipi_dsi_device(dev);
+	struct cwu50 *ctx = mipi_dsi_get_drvdata(dsi);
+
+	if (!ctx->dsi_status)
+		return scnprintf(buf, PAGE_SIZE, "ok\n");
+	else
+		return scnprintf(buf, PAGE_SIZE, "error\n");
+}
+
+static DEVICE_ATTR(dsi_state, 0444, dsi_state_show, NULL);
+
+static struct attribute *dsi_state_attrs[] = {
+	&dev_attr_dsi_state.attr,
+	NULL
+};
+
+static const struct attribute_group dsi_attr_group = {
+	.attrs = dsi_state_attrs,
+};
+
+static const struct drm_display_mode default_mode = {
+	.clock			= 61020,
+
+	.hdisplay		= 720,
+	.hsync_start	= 720    + 30,
+	.hsync_end		= 720    + 30  + 15,
+	.htotal			= 720    + 30  + 15  + 15,
+
+	.vdisplay		= 1280,
+	.vsync_start	= 1280   + 8,
+	.vsync_end		= 1280   + 8   + 2,
+	.vtotal			= 1280   + 8   + 2   + 16,
+
+	.width_mm		= 62,
+	.height_mm		= 110,
+	.type			= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+};
+
+static inline struct cwu50 *panel_to_cwu50(struct drm_panel *panel)
+{
+	return container_of(panel, struct cwu50, panel);
+}
+
+#define dcs_write_seq(seq...)                                       \
+({                                                                  \
+	static const u8 d[] = { seq };                                  \
+	err = mipi_dsi_dcs_write_buffer(dsi, d, ARRAY_SIZE(d));         \
+	if (err < 0)                                                    \
+		return err;                                                 \
+})
+
+static int cwu50_init_sequence(struct cwu50 *ctx)
+{
+	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+	int err;
+
+	dcs_write_seq(0xE1,0x93);
+	dcs_write_seq(0xE2,0x65);
+	dcs_write_seq(0xE3,0xF8);
+	dcs_write_seq(0x70,0x20);
+	dcs_write_seq(0x71,0x13);
+	dcs_write_seq(0x72,0x06);
+	dcs_write_seq(0x75,0x03);
+	dcs_write_seq(0xE0,0x01);
+	dcs_write_seq(0x00,0x00);
+	dcs_write_seq(0x01,0x47);//VCOM0x47
+	dcs_write_seq(0x03,0x00);
+	dcs_write_seq(0x04,0x4D);
+	dcs_write_seq(0x0C,0x64);
+	dcs_write_seq(0x17,0x00);
+	dcs_write_seq(0x18,0xBF);
+	dcs_write_seq(0x19,0x00);
+	dcs_write_seq(0x1A,0x00);
+	dcs_write_seq(0x1B,0xBF);
+	dcs_write_seq(0x1C,0x00);
+	dcs_write_seq(0x1F,0x7E);
+	dcs_write_seq(0x20,0x24);
+	dcs_write_seq(0x21,0x24);
+	dcs_write_seq(0x22,0x4E);
+	dcs_write_seq(0x24,0xFE);
+	dcs_write_seq(0x37,0x09);
+	dcs_write_seq(0x38,0x04);
+	dcs_write_seq(0x3C,0x76);
+	dcs_write_seq(0x3D,0xFF);
+	dcs_write_seq(0x3E,0xFF);
+	dcs_write_seq(0x3F,0x7F);
+	dcs_write_seq(0x40,0x04);//Dot inversion type
+	dcs_write_seq(0x41,0xA0);
+	dcs_write_seq(0x44,0x11);
+	dcs_write_seq(0x55,0x02);
+	dcs_write_seq(0x56,0x01);
+	dcs_write_seq(0x57,0x49);
+	dcs_write_seq(0x58,0x09);
+	dcs_write_seq(0x59,0x2A);
+	dcs_write_seq(0x5A,0x1A);
+	dcs_write_seq(0x5B,0x1A);
+	dcs_write_seq(0x5D,0x78);
+	dcs_write_seq(0x5E,0x6E);
+	dcs_write_seq(0x5F,0x66);
+	dcs_write_seq(0x60,0x5E);
+	dcs_write_seq(0x61,0x60);
+	dcs_write_seq(0x62,0x54);
+	dcs_write_seq(0x63,0x5C);
+	dcs_write_seq(0x64,0x47);
+	dcs_write_seq(0x65,0x5F);
+	dcs_write_seq(0x66,0x5D);
+	dcs_write_seq(0x67,0x5B);
+	dcs_write_seq(0x68,0x76);
+	dcs_write_seq(0x69,0x61);
+	dcs_write_seq(0x6A,0x63);
+	dcs_write_seq(0x6B,0x50);
+	dcs_write_seq(0x6C,0x45);
+	dcs_write_seq(0x6D,0x34);
+	dcs_write_seq(0x6E,0x1C);
+	dcs_write_seq(0x6F,0x07);
+	dcs_write_seq(0x70,0x78);
+	dcs_write_seq(0x71,0x6E);
+	dcs_write_seq(0x72,0x66);
+	dcs_write_seq(0x73,0x5E);
+	dcs_write_seq(0x74,0x60);
+	dcs_write_seq(0x75,0x54);
+	dcs_write_seq(0x76,0x5C);
+	dcs_write_seq(0x77,0x47);
+	dcs_write_seq(0x78,0x5F);
+	dcs_write_seq(0x79,0x5D);
+	dcs_write_seq(0x7A,0x5B);
+	dcs_write_seq(0x7B,0x76);
+	dcs_write_seq(0x7C,0x61);
+	dcs_write_seq(0x7D,0x63);
+	dcs_write_seq(0x7E,0x50);
+	dcs_write_seq(0x7F,0x45);
+	dcs_write_seq(0x80,0x34);
+	dcs_write_seq(0x81,0x1C);
+	dcs_write_seq(0x82,0x07);
+	dcs_write_seq(0xE0,0x02);
+	dcs_write_seq(0x00,0x44);
+	dcs_write_seq(0x01,0x46);
+	dcs_write_seq(0x02,0x48);
+	dcs_write_seq(0x03,0x4A);
+	dcs_write_seq(0x04,0x40);
+	dcs_write_seq(0x05,0x42);
+	dcs_write_seq(0x06,0x1F);
+	dcs_write_seq(0x07,0x1F);
+	dcs_write_seq(0x08,0x1F);
+	dcs_write_seq(0x09,0x1F);
+	dcs_write_seq(0x0A,0x1F);
+	dcs_write_seq(0x0B,0x1F);
+	dcs_write_seq(0x0C,0x1F);
+	dcs_write_seq(0x0D,0x1F);
+	dcs_write_seq(0x0E,0x1F);
+	dcs_write_seq(0x0F,0x1F);
+	dcs_write_seq(0x10,0x1F);
+	dcs_write_seq(0x11,0x1F);
+	dcs_write_seq(0x12,0x1F);
+	dcs_write_seq(0x13,0x1F);
+	dcs_write_seq(0x14,0x1E);
+	dcs_write_seq(0x15,0x1F);
+	dcs_write_seq(0x16,0x45);
+	dcs_write_seq(0x17,0x47);
+	dcs_write_seq(0x18,0x49);
+	dcs_write_seq(0x19,0x4B);
+	dcs_write_seq(0x1A,0x41);
+	dcs_write_seq(0x1B,0x43);
+	dcs_write_seq(0x1C,0x1F);
+	dcs_write_seq(0x1D,0x1F);
+	dcs_write_seq(0x1E,0x1F);
+	dcs_write_seq(0x1F,0x1F);
+	dcs_write_seq(0x20,0x1F);
+	dcs_write_seq(0x21,0x1F);
+	dcs_write_seq(0x22,0x1F);
+	dcs_write_seq(0x23,0x1F);
+	dcs_write_seq(0x24,0x1F);
+	dcs_write_seq(0x25,0x1F);
+	dcs_write_seq(0x26,0x1F);
+	dcs_write_seq(0x27,0x1F);
+	dcs_write_seq(0x28,0x1F);
+	dcs_write_seq(0x29,0x1F);
+	dcs_write_seq(0x2A,0x1E);
+	dcs_write_seq(0x2B,0x1F);
+	dcs_write_seq(0x2C,0x0B);
+	dcs_write_seq(0x2D,0x09);
+	dcs_write_seq(0x2E,0x07);
+	dcs_write_seq(0x2F,0x05);
+	dcs_write_seq(0x30,0x03);
+	dcs_write_seq(0x31,0x01);
+	dcs_write_seq(0x32,0x1F);
+	dcs_write_seq(0x33,0x1F);
+	dcs_write_seq(0x34,0x1F);
+	dcs_write_seq(0x35,0x1F);
+	dcs_write_seq(0x36,0x1F);
+	dcs_write_seq(0x37,0x1F);
+	dcs_write_seq(0x38,0x1F);
+	dcs_write_seq(0x39,0x1F);
+	dcs_write_seq(0x3A,0x1F);
+	dcs_write_seq(0x3B,0x1F);
+	dcs_write_seq(0x3C,0x1F);
+	dcs_write_seq(0x3D,0x1F);
+	dcs_write_seq(0x3E,0x1F);
+	dcs_write_seq(0x3F,0x1F);
+	dcs_write_seq(0x40,0x1F);
+	dcs_write_seq(0x41,0x1E);
+	dcs_write_seq(0x42,0x0A);
+	dcs_write_seq(0x43,0x08);
+	dcs_write_seq(0x44,0x06);
+	dcs_write_seq(0x45,0x04);
+	dcs_write_seq(0x46,0x02);
+	dcs_write_seq(0x47,0x00);
+	dcs_write_seq(0x48,0x1F);
+	dcs_write_seq(0x49,0x1F);
+	dcs_write_seq(0x4A,0x1F);
+	dcs_write_seq(0x4B,0x1F);
+	dcs_write_seq(0x4C,0x1F);
+	dcs_write_seq(0x4D,0x1F);
+	dcs_write_seq(0x4E,0x1F);
+	dcs_write_seq(0x4F,0x1F);
+	dcs_write_seq(0x50,0x1F);
+	dcs_write_seq(0x51,0x1F);
+	dcs_write_seq(0x52,0x1F);
+	dcs_write_seq(0x53,0x1F);
+	dcs_write_seq(0x54,0x1F);
+	dcs_write_seq(0x55,0x1F);
+	dcs_write_seq(0x56,0x1F);
+	dcs_write_seq(0x57,0x1E);
+	dcs_write_seq(0x58,0x40);
+	dcs_write_seq(0x59,0x00);
+	dcs_write_seq(0x5A,0x00);
+	dcs_write_seq(0x5B,0x30);
+	dcs_write_seq(0x5C,0x02);
+	dcs_write_seq(0x5D,0x40);
+	dcs_write_seq(0x5E,0x01);
+	dcs_write_seq(0x5F,0x02);
+	dcs_write_seq(0x60,0x00);
+	dcs_write_seq(0x61,0x01);
+	dcs_write_seq(0x62,0x02);
+	dcs_write_seq(0x63,0x65);
+	dcs_write_seq(0x64,0x66);
+	dcs_write_seq(0x65,0x00);
+	dcs_write_seq(0x66,0x00);
+	dcs_write_seq(0x67,0x74);
+	dcs_write_seq(0x68,0x06);
+	dcs_write_seq(0x69,0x65);
+	dcs_write_seq(0x6A,0x66);
+	dcs_write_seq(0x6B,0x10);
+	dcs_write_seq(0x6C,0x00);
+	dcs_write_seq(0x6D,0x04);
+	dcs_write_seq(0x6E,0x04);
+	dcs_write_seq(0x6F,0x88);
+	dcs_write_seq(0x70,0x00);
+	dcs_write_seq(0x71,0x00);
+	dcs_write_seq(0x72,0x06);
+	dcs_write_seq(0x73,0x7B);
+	dcs_write_seq(0x74,0x00);
+	dcs_write_seq(0x75,0x87);
+	dcs_write_seq(0x76,0x00);
+	dcs_write_seq(0x77,0x5D);
+	dcs_write_seq(0x78,0x17);
+	dcs_write_seq(0x79,0x1F);
+	dcs_write_seq(0x7A,0x00);
+	dcs_write_seq(0x7B,0x00);
+	dcs_write_seq(0x7C,0x00);
+	dcs_write_seq(0x7D,0x03);
+	dcs_write_seq(0x7E,0x7B);
+	dcs_write_seq(0xE0,0x04);
+	dcs_write_seq(0x09,0x10);
+	dcs_write_seq(0xE0,0x00);
+	dcs_write_seq(0xE6,0x02);
+	dcs_write_seq(0xE7,0x02);
+	// dcs_write_seq(0x11);// SLPOUT
+	// msleep (120);
+	// dcs_write_seq(0x29);// DSPON
+	// msleep (20);
+	// dcs_write_seq(0x35,0x00);// TE
+
+	return 0;
+}
+
+static int cwu50_unprepare(struct drm_panel *panel)
+{
+	struct cwu50 *ctx = panel_to_cwu50(panel);
+	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+	int err;
+
+	/* Power off the display using case 1 described in JD9365D.pdf chapter 9.5.3.
+	 * module's default behaviour
+	 */
+	if (1 == power_off_case) {
+		goto power_off_case1;
+	}
+
+	/* Power off the display using case 2 described in JD9365D.pdf chapter 9.5.3. */
+
+	/* tCMD_OFF >= 1ms */
+	msleep(1);
+
+	err = mipi_dsi_dcs_set_display_off(dsi);
+	if (err) {
+		dev_warn(ctx->dev, "failed to send display off command (%d)\n", err);
+		goto fallback_case1;
+	}
+
+	/* tDISOFF >= 50ms */
+	msleep(50);
+
+
+	err = mipi_dsi_dcs_enter_sleep_mode(dsi);
+	if (err) {
+		dev_warn(ctx->dev, "failed to enter sleep mode (%d)\n", err);
+		goto fallback_case1;
+	}
+
+	/* tSLPIN >= 100ms */
+	msleep(100);
+
+
+	gpiod_set_value_cansleep(ctx->reset_gpio, 1); /* assert reset */
+
+	goto disable_regulators;
+
+fallback_case1:
+	/* in case of error, fall back to case 1 */
+	dev_warn(ctx->dev, "falling back to power off case 1 using HW reset line");
+power_off_case1:
+	gpiod_set_value_cansleep(ctx->reset_gpio, 1); /* assert reset */
+	/* tRSTOFF1 >= 120ms */
+	msleep(120);
+
+disable_regulators:
+	regulator_disable(ctx->vci);
+	regulator_disable(ctx->iovcc);
+
+	return 0;
+}
+
+static int cwu50_prepare(struct drm_panel *panel)
+{
+	struct cwu50 *ctx = panel_to_cwu50(panel);
+	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+	int err;
+	u8 response;
+
+	gpiod_set_value_cansleep(ctx->reset_gpio, 1); /* ensure asserted state */
+
+	/* IOVCC first, then VCI */
+	err = regulator_enable(ctx->iovcc);
+	if (err) {
+		dev_err(ctx->dev, "failed to enable iovcc (%d)\n", err);
+		goto error_finialize;
+	}
+
+	/* tPWON>= 0ms */
+
+	/* MIPI should change to LP-11 after turning on vci according to JD9365D.pdf */
+	err = regulator_enable(ctx->vci);
+	if (err) {
+		dev_err(ctx->dev, "failed to enable vci (%d)\n", err);
+		goto disable_iovcc;
+	}
+
+	/* Wait for MIPI to initialize
+	 * tRPWIRES >= 5ms
+	 * 0 <= tMIPI_ON <= tRPWIRES
+	 */
+	msleep(30);
+
+	/* MIPI should be LP-11 now */
+
+	/* tRESETL=10us */
+	/* tRESETH >= 5ms */
+	gpiod_set_value_cansleep(ctx->reset_gpio, 0); /* deassert */
+	msleep(5);
+
+	/* Exit sleep mode and power on */
+
+	err = cwu50_init_sequence(ctx);
+	if (err) {
+		dev_err(ctx->dev, "failed to send initialize sequence (%d)\n", err);
+		goto disable_vci;
+	}
+
+	/* slpout */
+	err = mipi_dsi_dcs_exit_sleep_mode(dsi);
+	if (err) {
+		dev_err(ctx->dev, "failed to exit sleep mode (%d)\n", err);
+		goto disable_vci;
+	}
+
+	/* tSLPOUT 120ms */
+	msleep(120);
+
+	err = mipi_dsi_dcs_set_display_on(dsi);
+	if (err) {
+		dev_err(ctx->dev, "failed to turn display on (%d)\n", err);
+		goto disable_vci;
+	}
+	msleep(20);
+
+	/* Enabe tearing mode: send TE (tearing effect) at VBLANK */
+	/* JD9365D seems need a parameter for this command */
+	err = mipi_dsi_dcs_write_buffer(dsi, (u8[]){ 0x35, 0x00 }, 2);
+	// err = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
+	if (err < 0) {
+		dev_err(ctx->dev, "failed to enable vblank TE (%d)\n", err);
+		goto disable_vci;
+	}
+
+	err = mipi_dsi_dcs_get_power_mode(dsi, &response);
+	if (!err) {
+		/* debug, normally the command will fail */
+		dev_info(ctx->dev, "Read display power mode got: %d", response);
+	}
+
+	ctx->dsi_status = 0;  // ok
+
+	return 0;
+disable_vci:
+	regulator_disable(ctx->vci);
+disable_iovcc:
+	regulator_disable(ctx->iovcc);
+error_finialize:
+	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+	ctx->dsi_status = 1;
+	return err;
+}
+
+static int cwu50_get_modes(struct drm_panel *panel, struct drm_connector *connector)
+{
+	struct cwu50 *ctx = panel_to_cwu50(panel);
+	struct drm_display_mode *mode;
+
+	mode = drm_mode_duplicate(connector->dev, &default_mode);
+	if (!mode) {
+		dev_err(panel->dev, "bad mode or failed to add mode\n");
+		return -EINVAL;
+	}
+	drm_mode_set_name(mode);
+	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
+
+	/* set up connector's "panel orientation" property */
+	/*
+	 * TODO: Remove once all drm drivers call
+	 * drm_connector_set_orientation_from_panel()
+	 */
+	drm_connector_set_panel_orientation(connector, ctx->orientation);
+
+	drm_mode_probed_add(connector, mode);
+
+	return 1; /* Number of modes */
+}
+
+static enum drm_panel_orientation cwu50_get_orientation(struct drm_panel *panel)
+{
+	struct cwu50 *ctx = panel_to_cwu50(panel);
+
+	return ctx->orientation;
+}
+
+static const struct drm_panel_funcs cwu50_drm_funcs = {
+	.unprepare = cwu50_unprepare,
+	.prepare = cwu50_prepare,
+	.get_modes = cwu50_get_modes,
+	.get_orientation = cwu50_get_orientation,
+};
+
+static int cwu50_probe(struct mipi_dsi_device *dsi)
+{
+	struct device *dev = &dsi->dev;
+	struct cwu50 *ctx;
+	int err;
+
+	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
+	if (!ctx)
+		return -ENOMEM;
+
+	mipi_dsi_set_drvdata(dsi, ctx);
+	ctx->dev = dev;
+
+	dsi->lanes = 4;
+	dsi->format = MIPI_DSI_FMT_RGB888;
+	dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
+					  MIPI_DSI_MODE_VIDEO_BURST |
+					  MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
+
+	ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
+	if (IS_ERR(ctx->reset_gpio)) {
+		err = PTR_ERR(ctx->reset_gpio);
+		return dev_err_probe(dev, err, "Failed to request GPIO (%d)\n", err);
+	}
+
+	ctx->vci = devm_regulator_get(dev, "vci");
+	if (IS_ERR(ctx->vci)) {
+		err = PTR_ERR(ctx->vci);
+		return dev_err_probe(dev, err, "Failed to request vci regulator: %d\n", err);
+	}
+
+	ctx->iovcc = devm_regulator_get(dev, "iovcc");
+	if (IS_ERR(ctx->iovcc)) {
+		err = PTR_ERR(ctx->iovcc);
+		return dev_err_probe(dev, err, "Failed to request iovcc regulator: %d\n", err);
+	}
+
+	err = of_drm_get_panel_orientation(dev->of_node, &ctx->orientation);
+	if (err) {
+		dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
+		return err;
+	}
+
+	ctx->panel.prepare_prev_first = true;
+
+	drm_panel_init(&ctx->panel, dev, &cwu50_drm_funcs, DRM_MODE_CONNECTOR_DSI);
+
+	err = drm_panel_of_backlight(&ctx->panel);
+	if (err)
+		return dev_err_probe(dev, err, "Failed to get backlight\n");
+
+	drm_panel_add(&ctx->panel);
+
+	err = mipi_dsi_attach(dsi);
+	if (err < 0) {
+		dev_err(dev, "mipi_dsi_attach() failed: %d\n", err);
+		drm_panel_remove(&ctx->panel);
+		return err;
+	}
+
+	err = sysfs_create_group(&dsi->dev.kobj, &dsi_attr_group);
+	if (err < 0) {
+		dev_warn(dev, "Cannot create optional sysfs nodes: %d\n", err);
+	} else {
+		ctx->sysfs_node_created = true;
+	}
+
+	return 0;
+}
+
+static void cwu50_remove(struct mipi_dsi_device *dsi)
+{
+	struct cwu50 *ctx = mipi_dsi_get_drvdata(dsi);
+
+	if (ctx->sysfs_node_created) {
+		sysfs_remove_group(&dsi->dev.kobj, &dsi_attr_group);
+	}
+
+	mipi_dsi_detach(dsi);
+	drm_panel_remove(&ctx->panel);
+}
+
+static const struct of_device_id cwu50_of_match[] = {
+	{ .compatible = "clockwork,cwu50-cm3" },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, cwu50_of_match);
+
+static struct mipi_dsi_driver cwu50_driver = {
+	.probe = cwu50_probe,
+	.remove = cwu50_remove,
+	.driver = {
+		.name = "panel-clockwork-cwu50-cm3",
+		.of_match_table = cwu50_of_match,
+	},
+};
+module_mipi_dsi_driver(cwu50_driver);
+
+MODULE_DESCRIPTION("ClockworkPi CWU50-CM3 panel driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/panel/panel-cwu50.c b/drivers/gpu/drm/panel/panel-cwu50.c
new file mode 100644
index 000000000000..2d3cb79b1daf
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-cwu50.c
@@ -0,0 +1,846 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <drm/drm_modes.h>
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_panel.h>
+#include <linux/backlight.h>
+#include <linux/gpio/consumer.h>
+#include <linux/regulator/consumer.h>
+#include <linux/delay.h>
+#include <linux/of_device.h>
+#include <linux/module.h>
+
+struct cwu50 {
+	struct device *dev;
+	struct drm_panel panel;
+	struct regulator *vci;
+	struct regulator *iovcc;
+	struct gpio_desc *id_gpio;
+	struct backlight_device *backlight;
+	bool prepared;
+	bool enabled;
+	bool is_new_panel;
+	enum drm_panel_orientation orientation;
+};
+
+static const struct drm_display_mode default_mode = {
+	.clock = 61020,
+	.hdisplay = 720,
+	.hsync_start = 720 + 30,
+	.hsync_end = 720+ 30 + 15,
+	.htotal = 720 + 30 + 15 + 15,
+	.vdisplay = 1280,
+	.vsync_start = 1280 + 8,
+	.vsync_end = 1280 + 8+ 2,
+	.vtotal = 1280 + 8 + 2 + 16,
+};
+
+static inline struct cwu50 *panel_to_cwu50(struct drm_panel *panel)
+{
+	return container_of(panel, struct cwu50, panel);
+}
+
+#define dcs_write_seq(seq...)                              \
+({                                                              \
+	static const u8 d[] = { seq };                          \
+	mipi_dsi_dcs_write_buffer(dsi, d, ARRAY_SIZE(d));	 \
+})
+
+static void cwu50_init_sequence(struct cwu50 *ctx)
+{
+	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+
+	dcs_write_seq(0xE1,0x93);
+	dcs_write_seq(0xE2,0x65);
+	dcs_write_seq(0xE3,0xF8);
+	dcs_write_seq(0x70,0x20);
+	dcs_write_seq(0x71,0x13);
+	dcs_write_seq(0x72,0x06);
+	dcs_write_seq(0x75,0x03);
+	dcs_write_seq(0xE0,0x01);
+	dcs_write_seq(0x00,0x00);
+	dcs_write_seq(0x01,0x47);//VCOM0x47
+	dcs_write_seq(0x03,0x00);
+	dcs_write_seq(0x04,0x4D);
+	dcs_write_seq(0x0C,0x64);
+	dcs_write_seq(0x17,0x00);
+	dcs_write_seq(0x18,0xBF);
+	dcs_write_seq(0x19,0x00);
+	dcs_write_seq(0x1A,0x00);
+	dcs_write_seq(0x1B,0xBF);
+	dcs_write_seq(0x1C,0x00);
+	dcs_write_seq(0x1F,0x7E);
+	dcs_write_seq(0x20,0x24);
+	dcs_write_seq(0x21,0x24);
+	dcs_write_seq(0x22,0x4E);
+	dcs_write_seq(0x24,0xFE);
+	dcs_write_seq(0x37,0x09);
+	dcs_write_seq(0x38,0x04);
+	dcs_write_seq(0x3C,0x76);
+	dcs_write_seq(0x3D,0xFF);
+	dcs_write_seq(0x3E,0xFF);
+	dcs_write_seq(0x3F,0x7F);
+	dcs_write_seq(0x40,0x04);//Dot inversion type
+	dcs_write_seq(0x41,0xA0);
+	dcs_write_seq(0x44,0x11);
+	dcs_write_seq(0x55,0x02);
+	dcs_write_seq(0x56,0x01);
+	dcs_write_seq(0x57,0x49);
+	dcs_write_seq(0x58,0x09);
+	dcs_write_seq(0x59,0x2A);
+	dcs_write_seq(0x5A,0x1A);
+	dcs_write_seq(0x5B,0x1A);
+	dcs_write_seq(0x5D,0x78);
+	dcs_write_seq(0x5E,0x6E);
+	dcs_write_seq(0x5F,0x66);
+	dcs_write_seq(0x60,0x5E);
+	dcs_write_seq(0x61,0x60);
+	dcs_write_seq(0x62,0x54);
+	dcs_write_seq(0x63,0x5C);
+	dcs_write_seq(0x64,0x47);
+	dcs_write_seq(0x65,0x5F);
+	dcs_write_seq(0x66,0x5D);
+	dcs_write_seq(0x67,0x5B);
+	dcs_write_seq(0x68,0x76);
+	dcs_write_seq(0x69,0x61);
+	dcs_write_seq(0x6A,0x63);
+	dcs_write_seq(0x6B,0x50);
+	dcs_write_seq(0x6C,0x45);
+	dcs_write_seq(0x6D,0x34);
+	dcs_write_seq(0x6E,0x1C);
+	dcs_write_seq(0x6F,0x07);
+	dcs_write_seq(0x70,0x78);
+	dcs_write_seq(0x71,0x6E);
+	dcs_write_seq(0x72,0x66);
+	dcs_write_seq(0x73,0x5E);
+	dcs_write_seq(0x74,0x60);
+	dcs_write_seq(0x75,0x54);
+	dcs_write_seq(0x76,0x5C);
+	dcs_write_seq(0x77,0x47);
+	dcs_write_seq(0x78,0x5F);
+	dcs_write_seq(0x79,0x5D);
+	dcs_write_seq(0x7A,0x5B);
+	dcs_write_seq(0x7B,0x76);
+	dcs_write_seq(0x7C,0x61);
+	dcs_write_seq(0x7D,0x63);
+	dcs_write_seq(0x7E,0x50);
+	dcs_write_seq(0x7F,0x45);
+	dcs_write_seq(0x80,0x34);
+	dcs_write_seq(0x81,0x1C);
+	dcs_write_seq(0x82,0x07);
+	dcs_write_seq(0xE0,0x02);
+	dcs_write_seq(0x00,0x44);
+	dcs_write_seq(0x01,0x46);
+	dcs_write_seq(0x02,0x48);
+	dcs_write_seq(0x03,0x4A);
+	dcs_write_seq(0x04,0x40);
+	dcs_write_seq(0x05,0x42);
+	dcs_write_seq(0x06,0x1F);
+	dcs_write_seq(0x07,0x1F);
+	dcs_write_seq(0x08,0x1F);
+	dcs_write_seq(0x09,0x1F);
+	dcs_write_seq(0x0A,0x1F);
+	dcs_write_seq(0x0B,0x1F);
+	dcs_write_seq(0x0C,0x1F);
+	dcs_write_seq(0x0D,0x1F);
+	dcs_write_seq(0x0E,0x1F);
+	dcs_write_seq(0x0F,0x1F);
+	dcs_write_seq(0x10,0x1F);
+	dcs_write_seq(0x11,0x1F);
+	dcs_write_seq(0x12,0x1F);
+	dcs_write_seq(0x13,0x1F);
+	dcs_write_seq(0x14,0x1E);
+	dcs_write_seq(0x15,0x1F);
+	dcs_write_seq(0x16,0x45);
+	dcs_write_seq(0x17,0x47);
+	dcs_write_seq(0x18,0x49);
+	dcs_write_seq(0x19,0x4B);
+	dcs_write_seq(0x1A,0x41);
+	dcs_write_seq(0x1B,0x43);
+	dcs_write_seq(0x1C,0x1F);
+	dcs_write_seq(0x1D,0x1F);
+	dcs_write_seq(0x1E,0x1F);
+	dcs_write_seq(0x1F,0x1F);
+	dcs_write_seq(0x20,0x1F);
+	dcs_write_seq(0x21,0x1F);
+	dcs_write_seq(0x22,0x1F);
+	dcs_write_seq(0x23,0x1F);
+	dcs_write_seq(0x24,0x1F);
+	dcs_write_seq(0x25,0x1F);
+	dcs_write_seq(0x26,0x1F);
+	dcs_write_seq(0x27,0x1F);
+	dcs_write_seq(0x28,0x1F);
+	dcs_write_seq(0x29,0x1F);
+	dcs_write_seq(0x2A,0x1E);
+	dcs_write_seq(0x2B,0x1F);
+	dcs_write_seq(0x2C,0x0B);
+	dcs_write_seq(0x2D,0x09);
+	dcs_write_seq(0x2E,0x07);
+	dcs_write_seq(0x2F,0x05);
+	dcs_write_seq(0x30,0x03);
+	dcs_write_seq(0x31,0x01);
+	dcs_write_seq(0x32,0x1F);
+	dcs_write_seq(0x33,0x1F);
+	dcs_write_seq(0x34,0x1F);
+	dcs_write_seq(0x35,0x1F);
+	dcs_write_seq(0x36,0x1F);
+	dcs_write_seq(0x37,0x1F);
+	dcs_write_seq(0x38,0x1F);
+	dcs_write_seq(0x39,0x1F);
+	dcs_write_seq(0x3A,0x1F);
+	dcs_write_seq(0x3B,0x1F);
+	dcs_write_seq(0x3C,0x1F);
+	dcs_write_seq(0x3D,0x1F);
+	dcs_write_seq(0x3E,0x1F);
+	dcs_write_seq(0x3F,0x1F);
+	dcs_write_seq(0x40,0x1F);
+	dcs_write_seq(0x41,0x1E);
+	dcs_write_seq(0x42,0x0A);
+	dcs_write_seq(0x43,0x08);
+	dcs_write_seq(0x44,0x06);
+	dcs_write_seq(0x45,0x04);
+	dcs_write_seq(0x46,0x02);
+	dcs_write_seq(0x47,0x00);
+	dcs_write_seq(0x48,0x1F);
+	dcs_write_seq(0x49,0x1F);
+	dcs_write_seq(0x4A,0x1F);
+	dcs_write_seq(0x4B,0x1F);
+	dcs_write_seq(0x4C,0x1F);
+	dcs_write_seq(0x4D,0x1F);
+	dcs_write_seq(0x4E,0x1F);
+	dcs_write_seq(0x4F,0x1F);
+	dcs_write_seq(0x50,0x1F);
+	dcs_write_seq(0x51,0x1F);
+	dcs_write_seq(0x52,0x1F);
+	dcs_write_seq(0x53,0x1F);
+	dcs_write_seq(0x54,0x1F);
+	dcs_write_seq(0x55,0x1F);
+	dcs_write_seq(0x56,0x1F);
+	dcs_write_seq(0x57,0x1E);
+	dcs_write_seq(0x58,0x40);
+	dcs_write_seq(0x59,0x00);
+	dcs_write_seq(0x5A,0x00);
+	dcs_write_seq(0x5B,0x30);
+	dcs_write_seq(0x5C,0x02);
+	dcs_write_seq(0x5D,0x40);
+	dcs_write_seq(0x5E,0x01);
+	dcs_write_seq(0x5F,0x02);
+	dcs_write_seq(0x60,0x00);
+	dcs_write_seq(0x61,0x01);
+	dcs_write_seq(0x62,0x02);
+	dcs_write_seq(0x63,0x65);
+	dcs_write_seq(0x64,0x66);
+	dcs_write_seq(0x65,0x00);
+	dcs_write_seq(0x66,0x00);
+	dcs_write_seq(0x67,0x74);
+	dcs_write_seq(0x68,0x06);
+	dcs_write_seq(0x69,0x65);
+	dcs_write_seq(0x6A,0x66);
+	dcs_write_seq(0x6B,0x10);
+	dcs_write_seq(0x6C,0x00);
+	dcs_write_seq(0x6D,0x04);
+	dcs_write_seq(0x6E,0x04);
+	dcs_write_seq(0x6F,0x88);
+	dcs_write_seq(0x70,0x00);
+	dcs_write_seq(0x71,0x00);
+	dcs_write_seq(0x72,0x06);
+	dcs_write_seq(0x73,0x7B);
+	dcs_write_seq(0x74,0x00);
+	dcs_write_seq(0x75,0x87);
+	dcs_write_seq(0x76,0x00);
+	dcs_write_seq(0x77,0x5D);
+	dcs_write_seq(0x78,0x17);
+	dcs_write_seq(0x79,0x1F);
+	dcs_write_seq(0x7A,0x00);
+	dcs_write_seq(0x7B,0x00);
+	dcs_write_seq(0x7C,0x00);
+	dcs_write_seq(0x7D,0x03);
+	dcs_write_seq(0x7E,0x7B);
+	dcs_write_seq(0xE0,0x04);
+	dcs_write_seq(0x09,0x10);
+	dcs_write_seq(0xE0,0x00);
+	dcs_write_seq(0xE6,0x02);
+	dcs_write_seq(0xE7,0x02);
+}
+static int cwu50_init_sequence2(struct cwu50 *ctx)
+{
+	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+	int err;
+	dcs_write_seq(0xE0,0x00);
+
+	//--- PASSWORD	----//
+	dcs_write_seq(0xE1,0x93);
+	dcs_write_seq(0xE2,0x65);
+	dcs_write_seq(0xE3,0xF8);
+	dcs_write_seq(0x80,0x03);//03:4lane 02:3lane 01:2lane
+
+
+	//--- Page1  ----//
+	dcs_write_seq(0xE0,0x01);
+
+	//Set VCOM
+	dcs_write_seq(0x00,0x00);
+	dcs_write_seq(0x01,0x62);
+	dcs_write_seq(0x03,0x10);
+	dcs_write_seq(0x04,0x6A);
+
+	//Set Gamma Power, VGMP,VGMN,VGSP,VGSN
+	dcs_write_seq(0x17,0x00);
+	dcs_write_seq(0x18,0xDF); // VGMP=4.9V
+	dcs_write_seq(0x19,0x01); // VGSP=0.3V
+	dcs_write_seq(0x1A,0x00);
+	dcs_write_seq(0x1B,0xDF); // VGMN=-4.9V
+	dcs_write_seq(0x1C,0x01); // VGSN=0.3V
+
+	//VCL
+	dcs_write_seq(0x24,0xFE);
+
+	//Set Panel
+	dcs_write_seq(0x37,0x09);	//SS=1,BGR=1
+
+	//SET RGBCYC
+	dcs_write_seq(0x38,0x04);	//JDT=100 column inversion
+	dcs_write_seq(0x39,0x08);	//RGB_N_EQ1
+	dcs_write_seq(0x3A,0x12);	//RGB_N_EQ2
+	dcs_write_seq(0x3C,0x78);	//SET EQ3 for TE_H
+	dcs_write_seq(0x3D,0xFF);
+	dcs_write_seq(0x3E,0xFF);
+	dcs_write_seq(0x3F,0xFF);
+
+	//Set TCON
+	dcs_write_seq(0x40,0x04);	//RSO 04h=720, 05h=768, 06h=800
+	dcs_write_seq(0x41,0xA0);	//LN=640->1280 line
+	dcs_write_seq(0x42,0x7F);  //SLT=12.7us
+	dcs_write_seq(0x43,0x10);  //VFP
+	dcs_write_seq(0x44,0x17);  //VBP =24
+	dcs_write_seq(0x45,0x40);
+
+	//dcs_write_seq(0x4A,0x35);//BIST MODE 35:AUTO
+
+	//--- power voltage  ----//
+	dcs_write_seq(0x55,0x02);	//DCDCM=0011, JD5001
+	//dcs_write_seq(0x56,0x01);
+	dcs_write_seq(0x57,0x69);
+	//dcs_write_seq(0x58,0x0A);
+	dcs_write_seq(0x59,0x2A);	//VCL = -2.7V, AVEE=-5.5V
+	dcs_write_seq(0x5A,0x1A);	//VGH = +12.2V
+	dcs_write_seq(0x5B,0x1A);	//VGL = -12.2V
+
+	//--- Gamma2.2	----//	//G2.2	  //G2.5
+	dcs_write_seq(0x5D,0x7F);  //0x7F	//0x7F
+	dcs_write_seq(0x5E,0x67);  //0x67	//0x65
+	dcs_write_seq(0x5F,0x58);  //0x58	//0x55
+	dcs_write_seq(0x60,0x4B);  //0x4B	//0x47
+	dcs_write_seq(0x61,0x47);  //0x47	//0x42
+	dcs_write_seq(0x62,0x39);  //0x39	//0x32
+	dcs_write_seq(0x63,0x3D);  //0x3D	//0x36
+	dcs_write_seq(0x64,0x25);  //0x25	//0x1D
+	dcs_write_seq(0x65,0x3D);  //0x3D	//0x36
+	dcs_write_seq(0x66,0x3C);  //0x3C	//0x34
+	dcs_write_seq(0x67,0x3C);  //0x3C	//0x35
+	dcs_write_seq(0x68,0x5B);  //0x5B	//0x51
+	dcs_write_seq(0x69,0x4A);  //0x4A	//0x3D
+	dcs_write_seq(0x6A,0x50);  //0x50	//0x40
+	dcs_write_seq(0x6B,0x42);  //0x42	//0x31
+	dcs_write_seq(0x6C,0x3B);  //0x3B	//0x2C
+	dcs_write_seq(0x6D,0x2D);  //0x2D	//0x1F
+	dcs_write_seq(0x6E,0x19);  //0x19	//0x0E
+	dcs_write_seq(0x6F,0x00);  //0x00	//0x00
+	dcs_write_seq(0x70,0x7F);  //0x7F	//0x7F
+	dcs_write_seq(0x71,0x67);  //0x67	//0x65
+	dcs_write_seq(0x72,0x58);  //0x58	//0x55
+	dcs_write_seq(0x73,0x4B);  //0x4B	//0x47
+	dcs_write_seq(0x74,0x47);  //0x47	//0x42
+	dcs_write_seq(0x75,0x39);  //0x39	//0x32
+	dcs_write_seq(0x76,0x3D);  //0x3D	//0x36
+	dcs_write_seq(0x77,0x25);  //0x25	//0x1D
+	dcs_write_seq(0x78,0x3D);  //0x3D	//0x36
+	dcs_write_seq(0x79,0x3C);  //0x3C	//0x34
+	dcs_write_seq(0x7A,0x3C);  //0x3C	//0x35
+	dcs_write_seq(0x7B,0x5B);  //0x5B	//0x51
+	dcs_write_seq(0x7C,0x4A);  //0x4A	//0x3D
+	dcs_write_seq(0x7D,0x50);  //0x50	//0x40
+	dcs_write_seq(0x7E,0x42);  //0x42	//0x31
+	dcs_write_seq(0x7F,0x3B);  //0x3B	//0x2C
+	dcs_write_seq(0x80,0x2D);  //0x2D	//0x1F
+	dcs_write_seq(0x81,0x19);  //0x19	//0x0E
+	dcs_write_seq(0x82,0x00);  //0x00	//0x00
+
+
+	//Page2, for GIP
+	dcs_write_seq(0xE0,0x02);
+
+	//GIP_L Pin mapping
+	dcs_write_seq(0x00,0x5F);	//GCL
+	dcs_write_seq(0x01,0x5F);	//VSS->VGL
+	dcs_write_seq(0x02,0x44);	//CLK1->CKV0
+	dcs_write_seq(0x03,0x46);	//CKK3->CKV2
+	dcs_write_seq(0x04,0x48);	//CLK5->CKV4
+	dcs_write_seq(0x05,0x4A);	//CLK7->CKV6
+	dcs_write_seq(0x06,0x5F);	//VGL
+	dcs_write_seq(0x07,0x5F);	//VGL
+	dcs_write_seq(0x08,0x5F);	//VGL
+	dcs_write_seq(0x09,0x5F);	//NC
+	dcs_write_seq(0x0A,0x5F);	//NC
+	dcs_write_seq(0x0B,0x5F);	//NC //
+	dcs_write_seq(0x0C,0x5F);	//NC
+	dcs_write_seq(0x0D,0x5F);	//NC
+	dcs_write_seq(0x0E,0x5F);	//NC //
+	dcs_write_seq(0x0F,0x5F);	//NC
+	dcs_write_seq(0x10,0x5F);	//NC
+	dcs_write_seq(0x11,0x5F);	//NC //
+	dcs_write_seq(0x12,0x5E);	//GCH
+	dcs_write_seq(0x13,0x5E);	//VDD->VGH
+	dcs_write_seq(0x14,0x40);	//STV1
+	dcs_write_seq(0x15,0x42);	//STV3
+
+	//GIP_R Pin mapping
+	dcs_write_seq(0x16,0x5F);	//GCL
+	dcs_write_seq(0x17,0x5F);	//VSS->VGL
+	dcs_write_seq(0x18,0x45);	//CLK2->CKV1
+	dcs_write_seq(0x19,0x47);	//CKK4->CKV3
+	dcs_write_seq(0x1A,0x49);	//CLK6->CKV5
+	dcs_write_seq(0x1B,0x4B);	//CLK8->CKV7
+	dcs_write_seq(0x1C,0x5F);	//VGL
+	dcs_write_seq(0x1D,0x5F);	//VGL
+	dcs_write_seq(0x1E,0x5F);	//VGL
+	dcs_write_seq(0x1F,0x5F);	//NC
+	dcs_write_seq(0x20,0x5F);	//NC
+	dcs_write_seq(0x21,0x5F);	//NC //
+	dcs_write_seq(0x22,0x5F);	//NC
+	dcs_write_seq(0x23,0x5F);	//NC
+	dcs_write_seq(0x24,0x5F);	//NC //
+	dcs_write_seq(0x25,0x5F);	//NC
+	dcs_write_seq(0x26,0x5F);	//NC
+	dcs_write_seq(0x27,0x5F);	//NC //
+	dcs_write_seq(0x28,0x5E);	//GCH
+	dcs_write_seq(0x29,0x5E);	//VDD->VGH
+	dcs_write_seq(0x2A,0x41);	//STV2
+	dcs_write_seq(0x2B,0x43);	//STV4
+
+	//GIP_L_GS Pin mapping
+	dcs_write_seq(0x2C,0x1F);	//GCL
+	dcs_write_seq(0x2D,0x1E);	//VSS->VGH
+	dcs_write_seq(0x2E,0x0B);	//CLK1->CKV7
+	dcs_write_seq(0x2F,0x09);	//CKK3->CKV5
+	dcs_write_seq(0x30,0x07);	//CLK5->CKV3
+	dcs_write_seq(0x31,0x05);	//CLK7->CKV1
+	dcs_write_seq(0x32,0x1F);	//VGL
+	dcs_write_seq(0x33,0x1F);	//VGL
+	dcs_write_seq(0x34,0x1F);	//VGL
+	dcs_write_seq(0x35,0x1F);	//NC
+	dcs_write_seq(0x36,0x1F);	//NC
+	dcs_write_seq(0x37,0x1F);	//NC //
+	dcs_write_seq(0x38,0x1F);	//NC
+	dcs_write_seq(0x39,0x1F);	//NC
+	dcs_write_seq(0x3A,0x1F);	//NC //
+	dcs_write_seq(0x3B,0x1F);	//NC
+	dcs_write_seq(0x3C,0x1F);	//NC
+	dcs_write_seq(0x3D,0x1F);	//NC //
+	dcs_write_seq(0x3E,0x1E);	//GCH
+	dcs_write_seq(0x3F,0x1F);	//VDD->VGL
+	dcs_write_seq(0x40,0x03);	//STV1
+	dcs_write_seq(0x41,0x01);	//STV3
+
+	//GIP_R_GS Pin mapping
+	dcs_write_seq(0x42,0x1F);	//GCL
+	dcs_write_seq(0x43,0x1E);	//VSS->VGH
+	dcs_write_seq(0x44,0x0A);	//CLK2->CKV6
+	dcs_write_seq(0x45,0x08);	//CKK4->CKV4
+	dcs_write_seq(0x46,0x06);	//CLK6->CKV2
+	dcs_write_seq(0x47,0x04);	//CLK8->CKV0
+	dcs_write_seq(0x48,0x1F);	//VGL
+	dcs_write_seq(0x49,0x1F);	//VGL
+	dcs_write_seq(0x4A,0x1F);	//VGL
+	dcs_write_seq(0x4B,0x1F);	//NC
+	dcs_write_seq(0x4C,0x1F);	//NC
+	dcs_write_seq(0x4D,0x1F);	//NC //
+	dcs_write_seq(0x4E,0x1F);	//NC
+	dcs_write_seq(0x4F,0x1F);	//NC
+	dcs_write_seq(0x50,0x1F);	//NC //
+	dcs_write_seq(0x51,0x1F);	//NC
+	dcs_write_seq(0x52,0x1F);	//NC
+	dcs_write_seq(0x53,0x1F);	//NC //
+	dcs_write_seq(0x54,0x1E);	//GCH
+	dcs_write_seq(0x55,0x1F);	//VDD->VGL
+	dcs_write_seq(0x56,0x02);	//STV2
+	dcs_write_seq(0x57,0x00);	//STV4
+
+	//GIP Timing
+	dcs_write_seq(0x58,0x40);
+	dcs_write_seq(0x59,0x00);
+	dcs_write_seq(0x5A,0x00);
+	dcs_write_seq(0x5B,0x30);
+	dcs_write_seq(0x5C,0x0B); //STV_S0
+	dcs_write_seq(0x5D,0x30);
+	dcs_write_seq(0x5E,0x01);
+	dcs_write_seq(0x5F,0x02);
+	//dcs_write_seq(0x60,0x00);
+	//dcs_write_seq(0x61,0x01);
+	//dcs_write_seq(0x62,0x02);
+	dcs_write_seq(0x63,0x06);
+	dcs_write_seq(0x64,0x6A); //SETV_OFF
+	//dcs_write_seq(0x65,0x00);
+	//dcs_write_seq(0x66,0x00);
+	dcs_write_seq(0x67,0x73);
+	dcs_write_seq(0x68,0x0D); //CKV_S0
+	dcs_write_seq(0x69,0x06);
+	dcs_write_seq(0x6A,0x6A); //CKV_OFF,61(GOE=2.9)
+	dcs_write_seq(0x6B,0x10);
+	dcs_write_seq(0x6C,0x00);
+	dcs_write_seq(0x6D,0x04);
+	dcs_write_seq(0x6E,0x04);
+	dcs_write_seq(0x6F,0x88);
+	//dcs_write_seq(0x70,0x00);
+	//dcs_write_seq(0x71,0x00);
+	//dcs_write_seq(0x72,0x06);
+	//dcs_write_seq(0x73,0x7B);
+	//dcs_write_seq(0x74,0x00);
+	//dcs_write_seq(0x75,0x07);
+	//dcs_write_seq(0x76,0x00);
+	//dcs_write_seq(0x77,0x5D);
+	//dcs_write_seq(0x78,0x17);
+	//dcs_write_seq(0x79,0x1F);
+	//dcs_write_seq(0x7A,0x00);
+	//dcs_write_seq(0x7B,0x00);
+	//dcs_write_seq(0x7C,0x00);
+	//dcs_write_seq(0x7D,0x03);
+	//dcs_write_seq(0x7E,0x7B);
+
+	//Page4
+	dcs_write_seq(0xE0,0x04);
+	dcs_write_seq(0x00,0x0E);
+	dcs_write_seq(0x02,0xB3);
+	dcs_write_seq(0x09,0x60);
+	dcs_write_seq(0x0E,0x48);
+
+	//Page0
+	dcs_write_seq(0xE0,0x00);
+
+	dcs_write_seq(0x11);// SLPOUT
+	msleep (200);
+
+	dcs_write_seq(0x29);// DSiPON
+	msleep (100);
+
+
+	//--- TE----//
+	dcs_write_seq(0x35,0x00);
+
+	return 0;
+}
+
+static int cwu50_disable(struct drm_panel *panel)
+{
+	struct cwu50 *ctx = panel_to_cwu50(panel);
+	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+	int ret;
+
+	if (!ctx->enabled)
+		return 0;
+
+	backlight_disable(ctx->backlight);
+
+	ctx->enabled = false;
+
+	return 0;
+}
+
+static int cwu50_unprepare(struct drm_panel *panel)
+{
+	struct cwu50 *ctx = panel_to_cwu50(panel);
+	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+	int ret;
+
+	if (!ctx->prepared)
+		return 0;
+
+	ret = mipi_dsi_dcs_set_display_off(dsi);
+	if (ret) {
+		dev_err(ctx->dev, "failed to turn display off (%d)\n", ret);
+		return ret;
+	}
+
+	ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
+	if (ret) {
+		dev_err(ctx->dev, "failed to enter sleep mode (%d)\n", ret);
+		return ret;
+	}
+	msleep(120);
+
+	if (!ctx->is_new_panel) {
+		/* Assert reset on RESX */
+		dev_info(ctx->dev, "asserting reset pin for old panel\n");
+		gpiod_set_value_cansleep(ctx->id_gpio, 1);
+		msleep(5);
+	}
+
+	ctx->prepared = false;
+
+	return 0;
+}
+
+static int cwu50_prepare(struct drm_panel *panel)
+{
+	struct cwu50 *ctx = panel_to_cwu50(panel);
+	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+	int ret;
+	u8 buf[4];
+
+	if (ctx->prepared)
+		return 0;
+
+	if (ctx->iovcc != NULL && ctx->vci != NULL) {
+		dev_info(ctx->dev, "regulator iovcc and vci defined, enabling\n");
+
+		/* IOVCC first, then VCI */
+		ret = regulator_enable(ctx->iovcc);
+		if (ret) {
+			dev_err(ctx->dev, "failed to enable iovcc (%d)\n", ret);
+			return ret;
+		}
+
+		/* tPWON>= 0ms */
+
+		/* MIPI should change to LP-11 after turning on vci according to JD9365D.pdf */
+		ret = regulator_enable(ctx->vci);
+		if (ret) {
+			dev_err(ctx->dev, "failed to enable vci (%d)\n", ret);
+			regulator_disable(ctx->iovcc);
+			return ret;
+		}
+
+		/* Wait for MIPI to initialize
+		 * tRPWIRES >= 5ms
+		 * 0 <= tMIPI_ON <= tRPWIRES
+		 */
+		msleep(5);
+	}
+
+	if (!ctx->is_new_panel) {
+		dev_info(ctx->dev, "old panel, cycling the reset pin\n");
+		/* Cycle RESX (Hardware Reset) */
+		gpiod_set_value_cansleep(ctx->id_gpio, 1);
+		msleep(10);
+		gpiod_set_value_cansleep(ctx->id_gpio, 0);
+		msleep(5);
+	}
+
+	/* Enabe tearing mode: send TE (tearing effect) at VBLANK */
+	ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
+	if (ret) {
+		dev_err(ctx->dev, "failed to enable vblank TE (%d)\n", ret);
+		return ret;
+	}
+	/* Exit sleep mode and power on */
+	dcs_write_seq(0x11);// SLPOUT
+        msleep(120);
+        dcs_write_seq(0xE0,0x00);
+        mipi_dsi_dcs_read(dsi, 0x04, buf, 3);
+	
+        if(buf[0] == 0x39) ctx->is_new_panel = 1;
+
+	if (ctx->is_new_panel)
+		cwu50_init_sequence2(ctx);
+	else
+		cwu50_init_sequence(ctx);
+
+	ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
+	if (ret) {
+		dev_err(ctx->dev, "failed to exit sleep mode (%d)\n", ret);
+		return ret;
+	}
+	msleep(120);
+
+	ret = mipi_dsi_dcs_set_display_on(dsi);
+	if (ret) {
+		dev_err(ctx->dev, "failed to turn display on (%d)\n", ret);
+		return ret;
+	}
+	msleep(20);
+
+	ctx->prepared = true;
+
+	return 0;
+}
+
+static int cwu50_enable(struct drm_panel *panel)
+{
+	struct cwu50 *ctx = panel_to_cwu50(panel);
+	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+	int ret;
+
+	if (ctx->enabled)
+		return 0;
+
+	backlight_enable(ctx->backlight);
+
+	ctx->enabled = true;
+
+	return 0;
+}
+
+static int cwu50_get_modes(struct drm_panel *panel, struct drm_connector *connector)
+{
+	struct cwu50 *ctx = panel_to_cwu50(panel);
+	struct drm_display_mode *mode;
+
+	mode = drm_mode_duplicate(connector->dev, &default_mode);
+	if (!mode) {
+		dev_err(panel->dev, "bad mode or failed to add mode\n");
+		return -EINVAL;
+	}
+	drm_mode_set_name(mode);
+	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
+
+	connector->display_info.width_mm = mode->width_mm;
+	connector->display_info.height_mm = mode->height_mm;
+
+	/* set up connector's "panel orientation" property */
+	drm_connector_set_panel_orientation(connector, ctx->orientation);
+
+	drm_mode_probed_add(connector, mode);
+
+	return 1; /* Number of modes */
+}
+
+static const struct drm_panel_funcs cwu50_drm_funcs = {
+	.disable = cwu50_disable,
+	.unprepare = cwu50_unprepare,
+	.prepare = cwu50_prepare,
+	.enable = cwu50_enable,
+	.get_modes = cwu50_get_modes,
+};
+
+static int cwu50_probe(struct mipi_dsi_device *dsi)
+{
+	struct device *dev = &dsi->dev;
+	struct cwu50 *ctx;
+	int ret, err;
+
+	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
+	if (!ctx)
+		return -ENOMEM;
+
+	mipi_dsi_set_drvdata(dsi, ctx);
+	ctx->dev = dev;
+
+	dsi->lanes = 4;
+	dsi->format = MIPI_DSI_FMT_RGB888;
+	dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
+
+	ctx->id_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_IN);
+	if (IS_ERR(ctx->id_gpio)) {
+		ret = PTR_ERR(ctx->id_gpio);
+		if (ret != -EPROBE_DEFER)
+			dev_err(dev, "failed to request GPIO (%d)\n", ret);
+		return ret;
+	}
+
+	ctx->is_new_panel = gpiod_get_value_cansleep(ctx->id_gpio);
+	if (ctx->is_new_panel) {
+		dev_info(dev, "Detected new panel type\n");
+	} else {
+		dev_info(dev, "Detected old panel type\n");
+	}
+
+	/*
+	 * Switch the ID GPIO to OUTPUT for use with resetting,
+	 * only if we're using the old panel. The new panel's
+	 * ID (RESX) pin is always pulled down (or: asserted)
+	 * externally.
+	 */
+	if (!ctx->is_new_panel) {
+		dev_info(dev, "Old panel type, setting ID GPIO to OUTPUT for resetting\n");
+		ret = gpiod_direction_output(ctx->id_gpio, 0);
+
+		if (ret) {
+			dev_err(dev, "failed to set id_gpio to OUTPUT\n");
+			return ret;
+		}
+	}
+
+	/*
+	 * Request vci and iovcc regulators when they are defined
+	 * Even though these regulartors may be always-on, we still need
+	 * to ensure that the panel only becomes ready _after_ them.
+	 * This is achieved by bubbling up EPROBE_DEFER from them.
+	 */
+	ctx->vci = devm_regulator_get(dev, "vci");
+	if (IS_ERR(ctx->vci)) {
+		err = PTR_ERR(ctx->vci);
+		if (err == -EPROBE_DEFER) {
+			dev_info(dev, "vci regulator isn't ready, retry later\n");
+			return err;
+		}
+
+		dev_err(dev, "Failed to request vci regulator: %d\n", err);
+		ctx->vci = NULL;
+	}
+
+	ctx->iovcc = devm_regulator_get(dev, "iovcc");
+	if (IS_ERR(ctx->iovcc)) {
+		err = PTR_ERR(ctx->iovcc);
+		if (err == -EPROBE_DEFER) {
+			dev_info(dev, "iovcc regulator isn't ready, retry later\n");
+			return err;
+		}
+
+		dev_err(dev, "Failed to request iovcc regulator: %d\n", err);
+		ctx->iovcc = NULL;
+	}
+
+	ctx->backlight = devm_of_find_backlight(dev);
+	if (IS_ERR(ctx->backlight)) {
+		dev_err(ctx->dev, "devm_of_find_backlight");
+		return PTR_ERR(ctx->backlight);
+	}
+
+	ret = of_drm_get_panel_orientation(dev->of_node, &ctx->orientation);
+	if (ret) {
+		dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, ret);
+		return ret;
+	}
+
+	ctx->panel.prepare_prev_first = true;
+
+	drm_panel_init(&ctx->panel, dev, &cwu50_drm_funcs, DRM_MODE_CONNECTOR_DSI);
+
+	drm_panel_add(&ctx->panel);
+
+	ret = mipi_dsi_attach(dsi);
+	if (ret < 0) {
+		dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret);
+		drm_panel_remove(&ctx->panel);
+		return ret;
+	}
+
+	return 0;
+}
+
+static void cwu50_remove(struct mipi_dsi_device *dsi)
+{
+	struct cwu50 *ctx = mipi_dsi_get_drvdata(dsi);
+
+	mipi_dsi_detach(dsi);
+	drm_panel_remove(&ctx->panel);
+}
+
+static const struct of_device_id cwu50_of_match[] = {
+	{ .compatible = "cw,cwu50" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, cwu50_of_match);
+
+static struct mipi_dsi_driver cwu50_driver = {
+	.probe = cwu50_probe,
+	.remove = cwu50_remove,
+	.driver = {
+		.name = "panel-cwu50",
+		.of_match_table = cwu50_of_match,
+	},
+};
+module_mipi_dsi_driver(cwu50_driver);
+
+MODULE_DESCRIPTION("DRM Driver for cwu50 MIPI DSI panel");
+MODULE_LICENSE("GPL v2");
-- 
2.54.0

