Patches from:
- https://github.com/rk-unofficial-cfw/LibreELEC.tv/blob/le12-rk322x-wip/projects/Rockchip/devices/RK322X/patches/linux/default/linux-9000-rk322x-dts.patch
- https://github.com/rk-unofficial-cfw/LibreELEC.tv/blob/le12-rk322x-wip/projects/Rockchip/devices/RK322X/patches/linux/default/linux-9000-a95xr1-dts.patch

--- linux/arch/arm/boot/dts/rockchip/Makefile	2025-08-15 17:09:09.000000000 +0700
+++ linux-new/arch/arm/boot/dts/rockchip/Makefile	2025-08-23 17:11:46.308926827 +0700
@@ -16,6 +16,16 @@
 	rk3228-evb.dtb \
 	rk3229-evb.dtb \
 	rk3229-xms6.dtb \
+	rk322x-box.dtb \
+	rk322x-box-a95xr1.dtb \
+	rk322x-box-mxq4k.dtb \
+	rk322x-box-mxq4k_r29.dtb \
+	rk322x-box-mxq4kpro.dtb \
+	rk322x-box-mxq4kpro_r329q.dtb \
+	rk322x-box-onetv-lite.dtb \
+	rk322x-box-t95d.dtb \
+	rk322x-box-v884k.dtb \
+	rk322x-box-v88mars.dtb \
 	rk3288-evb-act8846.dtb \
 	rk3288-evb-rk808.dtb \
 	rk3288-firefly-beta.dtb \
diff -ruPN linux-old/arch/arm/boot/dts/rockchip/rk322x-box-a95xr1.dts linux/arch/arm/boot/dts/rockchip/rk322x-box-a95xr1.dts
--- /dev/null	2025-01-06 10:17:07.467999996 +0100
+++ linux/arch/arm/boot/dts/rockchip/rk322x-box-a95xr1.dts	2025-01-06 23:46:00.126768116 +0100
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include "rk322x-box.dtsi"
+#include "rk322x-opp.dtsi"
+#include "rk322x-legacy.dtsi"
+
+/ {
+	model = "RK3229 A95X-R1";
+	compatible = "rockchip,rk322x-box-a95xr1", "rockchip,rk3229";
+
+	leds {
+		compatible = "gpio-leds";
+
+		blue_led {
+			gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		red_led {
+			gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+			enable-state-shutdown;
+			linux,default-trigger = "rc-feedback";
+		};
+	};
+};
+
+&cpu0_opp_table {
+
+	opp-1104000000 {
+		status = "okay";
+	};
+
+	opp-1200000000 {
+		status = "okay";
+	};
+
+};
+
+&dmc {
+	status = "okay";
+};
+
+&dmc_opp_table {
+	opp-666000000 {
+		status = "okay";
+	};
+};
+
+&emmc {
+	status = "okay";
+};
+
diff -ruPN linux/arch/arm/boot/dts/rockchip/rk322x-box-mxq4k.dts linux-new/arch/arm/boot/dts/rockchip/rk322x-box-mxq4k.dts
--- linux/arch/arm/boot/dts/rockchip/rk322x-box-mxq4k.dts	1970-01-01 01:00:00.000000000 +0100
+++ linux-new/arch/arm/boot/dts/rockchip/rk322x-box-mxq4k.dts	2024-06-09 07:53:01.569912570 +0200
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include "rk322x-box.dtsi"
+#include "rk322x-opp.dtsi"
+#include "rk322x-legacy.dtsi"
+
+/ {
+	model = "RK3228 MXQ4K";
+	compatible = "rockchip,rk322x-box-mxq4k", "rockchip,rk3229";
+
+	leds {
+		compatible = "gpio-leds";
+
+		blue_led {
+			gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+		
+		red_led {
+			gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+                        enable-state-shutdown;
+                        linux,default-trigger = "rc-feedback";
+		};
+	};
+};
+
+&cpu0_opp_table {
+
+	opp-1104000000 {
+		status = "okay";
+	};
+
+	opp-1200000000 {
+		status = "okay";
+	};
+
+};
+
+&dmc {
+	status = "okay";
+};
+
+&dmc_opp_table {
+	opp-666000000 {
+		status = "okay";
+	};
+	
+	opp-728000000 {
+		status = "disabled";
+	};
+};
+
+&i2s1_bus {
+	rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
+			<0 RK_PB1 1 &pcfg_pull_none>,
+			<0 RK_PB3 1 &pcfg_pull_none>,
+			<0 RK_PB4 1 &pcfg_pull_none>,
+			<0 RK_PB5 1 &pcfg_pull_none>,
+			<0 RK_PB6 1 &pcfg_pull_none>,
+			<1 RK_PA4 2 &pcfg_pull_none>,
+			<1 RK_PA5 2 &pcfg_pull_none>;
+};
diff -ruPN linux/arch/arm/boot/dts/rockchip/rk322x-box-mxq4k_r29.dts linux-new/arch/arm/boot/dts/rockchip/rk322x-box-mxq4k_r29.dts
--- linux/arch/arm/boot/dts/rockchip/rk322x-box-mxq4k_r29.dts	1970-01-01 01:00:00.000000000 +0100
+++ linux-new/arch/arm/boot/dts/rockchip/rk322x-box-mxq4k_r29.dts	2024-05-15 19:17:00.274011021 +0200
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk322x-box.dtsi"
+#include "rk322x-opp.dtsi"
+#include "rk322x-legacy.dtsi"
+
+/ {
+	model = "RK3228 mxq4k box r29 variant";
+	compatible = "rockchip,rk322x-box-mxq4k_r29", "rockchip,rk3228";
+
+	leds {
+		compatible = "gpio-leds";
+
+		blue_led {
+			gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+		
+		red_led {
+			gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+			enable-state-shutdown;
+			linux,default-trigger = "rc-feedback";
+		};
+	};
+};
+
+&dmc {
+	status = "okay";
+};
+
+&emmc {
+	max-frequency = <50000000>;
+};
\ Manca newline alla fine del file
diff -ruPN linux/arch/arm/boot/dts/rockchip/rk322x-box-mxq4kpro.dts linux-new/arch/arm/boot/dts/rockchip/rk322x-box-mxq4kpro.dts
--- linux/arch/arm/boot/dts/rockchip/rk322x-box-mxq4kpro.dts	1970-01-01 01:00:00.000000000 +0100
+++ linux-new/arch/arm/boot/dts/rockchip/rk322x-box-mxq4kpro.dts	2023-12-02 07:39:23.903336405 +0100
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include "rk322x-box.dtsi"
+#include "rk322x-opp.dtsi"
+#include "rk322x-legacy.dtsi"
+
+/ {
+	model = "RK3228 MXQ4kpro box";
+	compatible = "rockchip,rk322x-box-mxq4kpro", "rockchip,rk3228";
+
+	leds {
+		compatible = "gpio-leds";
+
+		blue_led {
+			gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>;
+			default-state = "on";
+		};
+
+		red_led {
+			gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+			enable-state-shutdown;
+			linux,default-trigger = "rc-feedback";
+		};
+	};
+};
+
+&cpu0_opp_table {
+
+	opp-1104000000 {
+		status = "okay";
+	};
+
+	opp-1200000000 {
+		status = "okay";
+	};
+
+};
+
+&dmc {
+	status = "okay";
+};
+
+&dmc_opp_table {
+	opp-656000000 {
+		status = "okay";
+	};
+};
\ Manca newline alla fine del file
diff -ruPN linux/arch/arm/boot/dts/rockchip/rk322x-box-mxq4kpro_r329q.dts linux-new/arch/arm/boot/dts/rockchip/rk322x-box-mxq4kpro_r329q.dts
--- linux/arch/arm/boot/dts/rockchip/rk322x-box-mxq4kpro_r329q.dts	1970-01-01 01:00:00.000000000 +0100
+++ linux-new/arch/arm/boot/dts/rockchip/rk322x-box-mxq4kpro_r329q.dts	2023-12-02 07:39:38.178337003 +0100
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include "rk322x-box.dtsi"
+#include "rk322x-opp.dtsi"
+#include "rk322x-legacy.dtsi"
+
+/ {
+	model = "RK3228 MXQ4K with R329q board";
+	compatible = "rockchip,rk322x-box-mxq4k_r329q", "rockchip,rk3228";
+
+	leds {
+		compatible = "gpio-leds";
+
+		blue_led {
+			gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>;
+			default-state = "on";
+		};
+		
+		red_led {
+			gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+			linux,default-trigger = "rc-feedback";
+                        enable-state-shutdown;
+		};
+	};
+};
+
+&cpu0_opp_table {
+
+	opp-1104000000 {
+		status = "okay";
+	};
+
+	opp-1200000000 {
+		status = "okay";
+	};
+
+};
+
+&dmc {
+	status = "okay";
+};
+
+&dmc_opp_table {
+	opp-666000000 {
+		status = "okay";
+	};
+};
diff -ruPN linux/arch/arm/boot/dts/rockchip/rk322x-box-onetv-lite.dts linux-new/arch/arm/boot/dts/rockchip/rk322x-box-onetv-lite.dts
--- linux/arch/arm/boot/dts/rockchip/rk322x-box-onetv-lite.dts	1970-01-01 01:00:00.000000000 +0100
+++ linux-new/arch/arm/boot/dts/rockchip/rk322x-box-onetv-lite.dts	2023-12-02 07:39:50.921337536 +0100
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk322x-box.dtsi"
+#include "rk322x-opp.dtsi"
+#include "rk322x-legacy.dtsi"
+
+/ {
+	model = "RK3228 OneTv Lite";
+	compatible = "rockchip,rk322x-box-onetv-lite", "rockchip,rk3228";
+
+	leds {
+		compatible = "gpio-leds";
+
+		blue_led {
+			gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>;
+			default-state = "on";
+		};
+
+		red_led {
+                        gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>;
+                        default-state = "off";
+                        enable-state-shutdown;
+                        linux,default-trigger = "rc-feedback";
+                };
+	};
+};
+
+&dmc {
+	status = "okay";
+};
+
+&dmc_opp_table {
+        opp-666000000 {
+                status = "okay";
+        };
+};
+
+&dram_timing {
+	ddr3_drv = <DDR3_DS_34ohm>;
+	phy_ddr3_clk_drv = <PHY_DDR3_RON_RTT_22ohm>;
+	phy_ddr3_cmd_drv = <PHY_DDR3_RON_RTT_22ohm>;
+	phy_ddr3_dqs_drv = <PHY_DDR3_RON_RTT_22ohm>;
+};
diff -ruPN linux/arch/arm/boot/dts/rockchip/rk322x-box-t95d.dts linux-new/arch/arm/boot/dts/rockchip/rk322x-box-t95d.dts
--- linux/arch/arm/boot/dts/rockchip/rk322x-box-t95d.dts	1970-01-01 01:00:00.000000000 +0100
+++ linux-new/arch/arm/boot/dts/rockchip/rk322x-box-t95d.dts	2023-12-02 07:40:03.176338049 +0100
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk322x-box.dtsi"
+#include "rk322x-opp.dtsi"
+#include "rk322x-legacy.dtsi"
+
+/ {
+	model = "RK3228 T95D box";
+	compatible = "rockchip,rk322x-box-t95d", "rockchip,rk3228";
+
+	leds {
+		compatible = "gpio-leds";
+
+		blue_led {
+			gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+		
+		red_led {
+			gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+			enable-state-shutdown;
+			linux,default-trigger = "rc-feedback";
+		};
+	};
+	
+	openvfd {
+		compatible = "open,vfd";
+		dev_name = "openvfd";
+		status = "okay";
+	};
+};
+
+&dmc {
+	status = "okay";
+};
+
+&dram_timing {
+	sr_idle = <24>;
+	pd_idle = <32>;
+	ddr3_drv = <DDR3_DS_34ohm>;
+	ddr3_odt = <DDR3_ODT_120ohm>;
+	phy_ddr3_clk_drv = <PHY_DDR3_RON_RTT_34ohm>;
+	phy_ddr3_cmd_drv = <PHY_DDR3_RON_RTT_34ohm>;
+	phy_ddr3_dqs_drv = <PHY_DDR3_RON_RTT_34ohm>;
+	phy_ddr3_odt = <PHY_DDR3_RON_RTT_225ohm>;
+};
+
+&uart1 {
+	bluetooth {
+		compatible = "brcm,bcm4345c5";
+	};
+};
\ Manca newline alla fine del file
diff -ruPN linux/arch/arm/boot/dts/rockchip/rk322x-box-v884k.dts linux-new/arch/arm/boot/dts/rockchip/rk322x-box-v884k.dts
--- linux/arch/arm/boot/dts/rockchip/rk322x-box-v884k.dts	1970-01-01 01:00:00.000000000 +0100
+++ linux-new/arch/arm/boot/dts/rockchip/rk322x-box-v884k.dts	2023-12-02 07:40:25.720338993 +0100
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include "rk322x-box.dtsi"
+#include "rk322x-opp.dtsi"
+#include "rk322x-legacy.dtsi"
+
+/ {
+	model = "RK3228 V884K";
+	compatible = "rockchip,rk322x-box-v884k", "rockchip,rk3229";
+
+	leds {
+		compatible = "gpio-leds";
+
+		blue_led {
+			gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+	};
+};
+
+&cpu0_opp_table {
+
+	opp-1104000000 {
+		status = "okay";
+	};
+
+	opp-1200000000 {
+		status = "okay";
+	};
+
+};
+
+&dmc {
+	status = "okay";
+};
+
+&dmc_opp_table {
+	opp-666000000 {
+		status = "okay";
+	};
+};
\ Manca newline alla fine del file
diff -ruPN linux/arch/arm/boot/dts/rockchip/rk322x-box-v88mars.dts linux-new/arch/arm/boot/dts/rockchip/rk322x-box-v88mars.dts
--- linux/arch/arm/boot/dts/rockchip/rk322x-box-v88mars.dts	1970-01-01 01:00:00.000000000 +0100
+++ linux-new/arch/arm/boot/dts/rockchip/rk322x-box-v88mars.dts	2024-07-07 09:34:00.865380098 +0200
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include "rk322x-box.dtsi"
+#include "rk322x-opp.dtsi"
+#include "rk322x-legacy.dtsi"
+
+/ {
+	model = "RK3228 V88Mars";
+	compatible = "rockchip,rk322x-box-v88mars", "rockchip,rk3228";
+
+	leds {
+		compatible = "gpio-leds";
+
+		blue_led {
+			gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		red_led {
+			gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+			enable-state-shutdown;
+			linux,default-trigger = "rc-feedback";
+		};
+	};
+};
+
+&cpu0_opp_table {
+	opp-1104000000 {
+		status = "okay";
+	};
+
+	opp-1200000000 {
+		status = "okay";
+	};
+
+	opp-1296000000 {
+		status = "okay";
+	};
+	
+	opp-1392000000 {
+		status = "disabled";
+	};
+};
diff -ruPN linux/arch/arm/boot/dts/rockchip/rk322x-box.dts linux-new/arch/arm/boot/dts/rockchip/rk322x-box.dts
--- linux/arch/arm/boot/dts/rockchip/rk322x-box.dts	1970-01-01 01:00:00.000000000 +0100
+++ linux-new/arch/arm/boot/dts/rockchip/rk322x-box.dts	2024-05-15 19:16:05.179008715 +0200
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk322x-box.dtsi"
+#include "rk322x-opp.dtsi"
+#include "rk322x-legacy.dtsi"
+
+/ {
+        model = "Generic rk322x tv box";
+        compatible = "rockchip,rk3228", "rockchip,rk322x-box";
+/*
+	leds {
+		compatible = "gpio-leds";
+
+		blue_led {
+			gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		red_led {
+                        gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                        enable-state-shutdown;
+                };
+	};
+*/
+};
+
+&emmc {
+	max-frequency = <50000000>;
+};
\ Manca newline alla fine del file
diff -ruPN linux/arch/arm/boot/dts/rockchip/rk322x-box.dtsi linux-new/arch/arm/boot/dts/rockchip/rk322x-box.dtsi
--- linux/arch/arm/boot/dts/rockchip/rk322x-box.dtsi	1970-01-01 01:00:00.000000000 +0100
+++ linux-new/arch/arm/boot/dts/rockchip/rk322x-box.dtsi	2024-05-15 19:14:46.332005414 +0200
@@ -0,0 +1,481 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include <dt-bindings/input/input.h>
+#include "rk322x.dtsi"
+
+/ {
+
+	aliases {
+		mmc0 = &sdmmc;
+		mmc2 = &sdio;
+		mmc1 = &emmc;
+	};
+
+	dc_12v: dc-12v-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_12v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	ext_gmac: ext_gmac {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "ext_gmac";
+		#clock-cells = <0>;
+	};
+
+	hdmi_sound: hdmi-sound {
+		status = "okay";
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "HDMI";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,mclk-fs = <256>;
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s0>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&hdmi>;
+		};
+	};
+
+	ir_receiver: ir-receiver {
+		compatible = "rockchip-ir-receiver";
+		reg = <0x110b0030 0x10>;
+		gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_LOW>;
+		clocks = <&cru PCLK_PWM>;
+		interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+		pinctrl-names = "default", "suspend";
+		pinctrl-0 = <&ir_int>;
+		pinctrl-1 = <&pwm3_pin>;
+		pwm-id = <3>;
+		shutdown-is-virtual-poweroff;
+		status = "okay";
+	};
+
+	memory@60000000 {
+		device_type = "memory";
+		reg = <0x60000000 0x40000000>;
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		/*pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;*/
+		post-power-on-delay-ms = <100>;
+		power-off-delay-us = <100000>;
+		reset-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_LOW>,
+			      <&gpio2 RK_PD5 GPIO_ACTIVE_LOW>,
+			      <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
+	};
+
+	spdif_out: spdif-out {
+		status = "okay";
+		compatible = "linux,spdif-dit";
+		#sound-dai-cells = <0>;
+	};
+
+	spdif-sound {
+		status = "okay";
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "SPDIF";
+
+		simple-audio-card,cpu {
+			sound-dai = <&spdif>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&spdif_out>;
+		};
+	};
+
+	vcc_sys: vcc-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc_host: vcc-host-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&host_vbus_drv>;
+		regulator-name = "vcc_host";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc_sys>;
+	};
+
+	vccio_1v8: vccio-1v8-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vccio_1v8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+		vin-supply = <&vcc_sys>;
+	};
+
+	vccio_0v9: vccio-0v9-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vccio_0v9";
+		regulator-min-microvolt = <900000>;
+		regulator-max-microvolt = <900000>;
+		regulator-always-on;
+		vin-supply = <&vcc_sys>;
+	};
+
+	vcc_phy: vcc-phy-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		regulator-name = "vcc_phy";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vccio_1v8>;
+	};
+
+	vccio_3v3: vccio-3v3-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vccio_3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		vin-supply = <&vcc_sys>;
+	};
+
+	vdd_arm: vdd-arm-regulator {
+		compatible = "pwm-regulator";
+		pwms = <&pwm1 0 25000 1>;
+		pwm-supply = <&vcc_sys>;
+		regulator-name = "vdd_arm";
+		regulator-min-microvolt = <950000>;
+		regulator-max-microvolt = <1400000>;
+		regulator-ramp-delay = <4000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vdd_hdmi_phy: vdd-hdmi-phy-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "hack_to_enable_some_hdmi_connector";
+		gpio = <&gpio2 RK_PB3 GPIO_ACTIVE_LOW>;
+		pinctrl-0 = <&hdmi_phy_enable>;
+		pinctrl-names = "default";
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc_sys>;
+	};
+
+	vdd_log: vdd-log-regulator {
+		compatible = "pwm-regulator";
+		pwms = <&pwm2 0 25000 1>;
+		pwm-supply = <&vcc_sys>;
+		regulator-name = "vdd_log";
+		regulator-min-microvolt = <1000000>;
+		regulator-max-microvolt = <1300000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_arm>;
+	clock-frequency = <1200000000>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_arm>;
+	clock-frequency = <1200000000>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_arm>;
+	clock-frequency = <1200000000>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_arm>;
+	clock-frequency = <1200000000>;
+};
+
+&cpu_alert0 {
+	temperature = <85000>;
+};
+
+&cpu_alert1 {
+	temperature = <95000>;
+};
+
+&cpu_crit {
+	temperature = <105000>;
+};
+
+&cru {
+    assigned-clocks = <&cru PLL_GPLL>, <&cru ARMCLK>,
+		<&cru PLL_CPLL>, <&cru ACLK_PERI>,
+		<&cru HCLK_PERI>, <&cru PCLK_PERI>,
+		<&cru ACLK_CPU>, <&cru HCLK_CPU>,
+		<&cru PCLK_CPU>, <&cru ACLK_VOP>;
+
+    assigned-clock-rates = <1200000000>, <816000000>,
+			    <500000000>, <150000000>,
+			    <150000000>, <75000000>,
+			    <150000000>, <150000000>,
+			    <75000000>, <400000000>;
+};
+
+&crypto {
+	assigned-clocks = <&cru HCLK_M_CRYPTO>;
+	assigned-clock-rates = <200000000>;
+};
+
+&emmc {
+	/delete-property/ pinctrl-names;
+	/delete-property/ pinctrl-0;
+	/delete-property/ rockchip,default-sample-phase;
+
+	cap-mmc-highspeed;
+	non-removable;
+	status = "okay";
+};
+
+&gmac {
+	assigned-clocks = <&cru SCLK_MAC_SRC>;
+	assigned-clock-rates = <50000000>;
+	clock_in_out = "output";
+	phy-handle = <&phy>;
+	phy-mode = "rmii";
+	phy-supply = <&vcc_phy>;
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		phy: ethernet-phy@0 {
+			compatible = "ethernet-phy-id1234.d400",
+			             "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+			clocks = <&cru SCLK_MAC_PHY>;
+			phy-is-integrated;
+			resets = <&cru SRST_MACPHY>;
+		};
+	};
+};
+
+&gpu {
+	mali-supply = <&vdd_log>;
+	status = "okay";
+};
+
+&hdmi {
+	avdd-0v9-supply = <&vccio_0v9>;
+	avdd-1v8-supply = <&vccio_1v8>;
+	status = "okay";
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&hdmi_phy {
+	status = "okay";
+};
+
+&i2s0 {
+	status = "okay";
+};
+
+&iep {
+	status = "okay";
+};
+
+&iep_mmu {
+	status = "okay";
+};
+
+&io_domains {
+	status = "okay";
+
+	vccio1-supply = <&vccio_3v3>;
+	vccio2-supply = <&vccio_1v8>;
+	vccio4-supply = <&vccio_3v3>;
+};
+
+&pinctrl {
+
+	hdmi-phy {
+		hdmi_phy_enable: hdmi-phy-enable {
+			rockchip,pins = <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	ir {
+		ir_int: ir-int {
+			rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb {
+		host_vbus_drv: host-vbus-drv {
+			rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pwm1 {
+	status = "okay";
+};
+
+&pwm2 {
+	status = "okay";
+};
+
+&sdio {
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	keep-power-in-suspend;
+	no-sd;
+	no-mmc;
+	status = "okay";
+};
+
+&sdmmc {
+	cap-sd-highspeed;
+	status = "okay";
+	cd-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_LOW>;
+	cd-debounce-delay-ms = <500>;
+};
+
+&spdif {
+	status = "okay";
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <0>;
+	rockchip,grf = <&grf>;
+	rockchip,hw-tshut-polarity = <1>;
+	rockchip,hw-tshut-temp = <105000>;
+	
+	/* delete the pinctrl-* properties because, on mainline kernel, they (in particular "default")
+	   change the GPIO configuration of the associated PIN. On most boards that pin is not connected
+	   so it does not do anything, but some other boards (X96-Mini) have that pin connected to
+	   a reset pin of the soc or whatever, thus changing the configuration of the pin at boot 
+	   causes them to bootloop.
+	   We don't really need these ones though, because since hw-tshut-mode is set to 0, the CRU
+	   unit of the SoC does the reboot*/
+
+	/delete-property/ pinctrl-names;
+	/delete-property/ pinctrl-0;
+	/delete-property/ pinctrl-1;
+	/delete-property/ pinctrl-2;
+
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+
+	u2phy0_host: host-port {
+		phy-supply = <&vcc_host>;
+		status = "okay";
+	};
+
+	u2phy0_otg: otg-port {
+		phy-supply = <&vcc_host>;
+		status = "okay";
+	};
+};
+
+&u2phy1 {
+	status = "okay";
+
+	u2phy1_host: host-port {
+		phy-supply = <&vcc_host>;
+		status = "okay";
+	};
+
+	u2phy1_otg: otg-port {
+		phy-supply = <&vcc_host>;
+		status = "okay";
+	};
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart11_xfer &uart11_rts &uart11_cts>;
+	uart-has-rtscts;
+	status = "okay";
+	bluetooth {
+		enable-gpios = <&gpio2 RK_PD5 GPIO_ACTIVE_HIGH>;
+		device-wake-gpios = <&gpio3 RK_PD3 GPIO_ACTIVE_HIGH>;
+		host-wake-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usb_host2_ehci {
+	status = "okay";
+};
+
+&usb_host2_ohci {
+	status = "okay";
+};
+
+&usb_otg {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&vdec {
+	/*assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
+	assigned-clock-rates = <300000000>, <300000000>, <300000000>;*/
+};
+
+&vop {
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
diff -ruPN linux/arch/arm/boot/dts/rockchip/rk322x-legacy.dtsi linux-new/arch/arm/boot/dts/rockchip/rk322x-legacy.dtsi
--- linux/arch/arm/boot/dts/rockchip/rk322x-legacy.dtsi	1970-01-01 01:00:00.000000000 +0100
+++ linux-new/arch/arm/boot/dts/rockchip/rk322x-legacy.dtsi	2023-10-15 08:08:18.495034516 +0200
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/ {
+
+	analog_sound: analog-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,name = "Analog";
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s1>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&codec>;
+		};
+	};
+
+	nandc: nandc@30030000 {
+		compatible = "rockchip,rk-nandc";
+		reg = <0x30030000 0x4000>;
+		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+		nandc_id = <0>;
+		clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>;
+		clock-names = "clk_nandc", "hclk_nandc";
+		status = "disabled";
+	};
+
+};
+
+&codec {
+	#sound-dai-cells = <0>;
+	status = "okay";
+};
+
+&dmc {
+	logic-supply = <&vdd_log>;
+	status = "disabled";
+};
+
+&i2s1 {
+	status = "okay";
+};
+
+/*&nandc {
+	status = "okay";
+};*/
diff -ruPN linux/arch/arm/boot/dts/rockchip/rk322x-opp.dtsi linux-new/arch/arm/boot/dts/rockchip/rk322x-opp.dtsi
--- linux/arch/arm/boot/dts/rockchip/rk322x-opp.dtsi	1970-01-01 01:00:00.000000000 +0100
+++ linux-new/arch/arm/boot/dts/rockchip/rk322x-opp.dtsi	2024-07-10 16:39:49.606789179 +0200
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/ {
+	/delete-node/ opp-table-0;
+
+	cpu0_opp_table: opp-table-0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+		nvmem-cells = <&cpu_leakage>;
+		nvmem-cell-names = "cpu-leakage";
+
+		opp-408000000 {
+			opp-hz = /bits/ 64 <408000000>;
+			opp-microvolt = <975000 975000 1275000>;
+			opp-microvolt-L0 = <975000 975000 1275000>;
+			opp-microvolt-L1 = <975000 975000 1275000>;
+			opp-suspend;
+		};
+		opp-600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <1000000 1000000 1275000>;
+			opp-microvolt-L0 = <1000000 1000000 1275000>;
+			opp-microvolt-L1 = <975000 975000 1275000>;
+		};
+		opp-696000000 {
+			opp-hz = /bits/ 64 <696000000>;
+			opp-microvolt = <1000000 1000000 1275000>;
+			opp-microvolt-L0 = <1025000 1025000 1275000>;
+			opp-microvolt-L1 = <1000000 1000000 1275000>;
+		};
+		opp-816000000 {
+			opp-hz = /bits/ 64 <816000000>;
+			opp-microvolt = <1025000 1025000 1275000>;
+			opp-microvolt-L0 = <1025000 1025000 1275000>;
+			opp-microvolt-L1 = <1000000 1000000 1275000>;
+		};
+		opp-1008000000 {
+			opp-hz = /bits/ 64 <1008000000>;
+			opp-microvolt = <1075000 1075000 1275000>;
+			opp-microvolt-L0 = <1075000 1075000 1275000>;
+			opp-microvolt-L1 = <1025000 1025000 1275000>;
+		};
+		opp-1104000000 {
+			opp-hz = /bits/ 64 <1104000000>;
+			opp-microvolt = <1125000 1125000 1275000>;
+			opp-microvolt-L0 = <1125000 1125000 1275000>;
+			opp-microvolt-L1 = <1075000 1075000 1275000>;
+			status = "disabled";
+		};
+		opp-1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <1175000 1175000 1275000>;
+			opp-microvolt-L0 = <1175000 1175000 1275000>;
+			opp-microvolt-L1 = <1125000 1125000 1275000>;
+			status = "disabled";
+		};
+		opp-1296000000 {
+			opp-hz = /bits/ 64 <1296000000>;
+			opp-microvolt = <1225000 1225000 1275000>;
+			opp-microvolt-L0 = <1225000 1225000 1275000>;
+			opp-microvolt-L1 = <1175000 1175000 1275000>;
+			status = "disabled";
+		};
+		opp-1392000000 {
+			opp-hz = /bits/ 64 <1392000000>;
+			opp-microvolt = <1275000 1275000 1275000>;
+			opp-microvolt-L0 = <1275000 1275000 1275000>;
+			opp-microvolt-L1 = <1225000 1225000 1275000>;
+			status = "disabled";
+		};
+	};
+	
+	/delete-node/ dmc-opp-table;
+
+	dmc_opp_table: dmc-opp-table {
+		compatible = "operating-points-v2";
+
+		opp-330000000 {
+			opp-hz = /bits/ 64 <330000000>;
+			opp-microvolt = <1050000 1050000 1200000>;
+		};
+		opp-400000000 {
+			opp-hz = /bits/ 64 <400000000>;
+			opp-microvolt = <1050000 1050000 1200000>;
+		};
+		opp-666000000 {
+			opp-hz = /bits/ 64 <666000000>;
+			opp-microvolt = <1075000 1075000 1200000>;
+			status = "disabled";
+		};
+		opp-728000000 {
+			opp-hz = /bits/ 64 <728000000>;
+			opp-microvolt = <1125000 1125000 1200000>;
+			status = "disabled";
+		};
+
+	};
+
+	/delete-node/ opp-table2;
+
+	gpu_opp_table: opp-table2 {
+		compatible = "operating-points-v2";
+
+		opp-200000000 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-microvolt = <1050000 1050000 1200000>;
+		};
+
+		opp-300000000 {
+			opp-hz = /bits/ 64 <300000000>;
+			opp-microvolt = <1050000 1050000 1200000>;
+		};
+		
+		opp-400000000 {
+			opp-hz = /bits/ 64 <400000000>;
+			opp-microvolt = <1075000 1075000 1200000>;
+		};
+		
+		opp-500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			opp-microvolt = <1125000 1125000 1200000>;
+			status = "disabled";
+		};
+	};
+};
+
+&cpu_thermal {
+	cooling-maps {
+		map0 {
+			trip = <&cpu_alert0>;
+			cooling-device = <&cpu0 THERMAL_NO_LIMIT 2>,
+				<&cpu1 THERMAL_NO_LIMIT 2>,
+				<&cpu2 THERMAL_NO_LIMIT 2>,
+				<&cpu3 THERMAL_NO_LIMIT 2>;
+		};
+
+		map1 {
+			trip = <&cpu_alert1>;
+			cooling-device = <&cpu0 THERMAL_NO_LIMIT 4>,
+				<&cpu1 THERMAL_NO_LIMIT 4>,
+				<&cpu2 THERMAL_NO_LIMIT 4>,
+				<&cpu3 THERMAL_NO_LIMIT 4>;
+		};
+
+		map2 {
+			trip = <&cpu_alert1>;
+			cooling-device =
+			<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+		};
+		
+		map3 {
+			trip = <&cpu_alert1>;
+			cooling-device =
+			<&dmc THERMAL_NO_LIMIT 1>;
+		};
+	};
+};
