83856aaab4
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Whilst here, move the marking to cover the whole union. That has no functional affect, but makes it slightly easier to see what is going on. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20220813160600.1157169-1-jic23@kernel.org |
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| .. | ||
| accel | ||
| adc | ||
| addac | ||
| Documentation | ||
| frequency | ||
| impedance-analyzer | ||
| meter | ||
| resolver | ||
| Kconfig | ||
| Makefile | ||
| TODO | ||