23ed2be540
imx93 A0 chip use the internal q-channel handshake signal in LPCG and CCM to automatically handle the Flex-CAN stop mode. But this method meet issue when do the system PM stress test. IC can't fix it easily. So in the new imx93 A1 chip, IC drop this method, and involve back the old way，use the GPR method to trigger the Flex-CAN stop mode signal. Now NXP claim to drop imx93 A0, and only support imx93 A1. So here add the stop mode through GPR. This patch also fix a typo for aonmix_ns_gpr. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Link: https://lore.kernel.org/all/20230726112458.3524165-1-haibo.chen@nxp.com Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
928 lines
25 KiB
Text
928 lines
25 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2022 NXP
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*/
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#include <dt-bindings/clock/imx93-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/fsl,imx93-power.h>
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#include <dt-bindings/thermal/thermal.h>
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#include "imx93-pinfunc.h"
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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gpio0 = &gpio1;
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gpio1 = &gpio2;
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gpio2 = &gpio3;
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gpio3 = &gpio4;
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i2c0 = &lpi2c1;
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i2c1 = &lpi2c2;
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i2c2 = &lpi2c3;
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i2c3 = &lpi2c4;
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i2c4 = &lpi2c5;
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i2c5 = &lpi2c6;
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i2c6 = &lpi2c7;
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i2c7 = &lpi2c8;
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mmc0 = &usdhc1;
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mmc1 = &usdhc2;
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mmc2 = &usdhc3;
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serial0 = &lpuart1;
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serial1 = &lpuart2;
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serial2 = &lpuart3;
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serial3 = &lpuart4;
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serial4 = &lpuart5;
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serial5 = &lpuart6;
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serial6 = &lpuart7;
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serial7 = &lpuart8;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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idle-states {
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entry-method = "psci";
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cpu_pd_wait: cpu-pd-wait {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x0010033>;
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local-timer-stop;
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entry-latency-us = <10000>;
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exit-latency-us = <7000>;
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min-residency-us = <27000>;
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wakeup-latency-us = <15000>;
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};
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};
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A55_0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0>;
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enable-method = "psci";
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#cooling-cells = <2>;
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cpu-idle-states = <&cpu_pd_wait>;
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};
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A55_1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x100>;
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enable-method = "psci";
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#cooling-cells = <2>;
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cpu-idle-states = <&cpu_pd_wait>;
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};
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};
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osc_32k: clock-osc-32k {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "osc_32k";
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};
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osc_24m: clock-osc-24m {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "osc_24m";
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};
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clk_ext1: clock-ext1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <133000000>;
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clock-output-names = "clk_ext1";
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};
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pmu {
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compatible = "arm,cortex-a55-pmu";
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interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <24000000>;
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arm,no-tick-in-suspend;
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interrupt-parent = <&gic>;
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};
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gic: interrupt-controller@48000000 {
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compatible = "arm,gic-v3";
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reg = <0 0x48000000 0 0x10000>,
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<0 0x48040000 0 0xc0000>;
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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};
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thermal-zones {
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cpu-thermal {
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polling-delay-passive = <250>;
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polling-delay = <2000>;
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thermal-sensors = <&tmu 0>;
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trips {
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cpu_alert: cpu-alert {
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temperature = <80000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit: cpu-crit {
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temperature = <90000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu_alert>;
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cooling-device =
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<&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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};
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cm33: remoteproc-cm33 {
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compatible = "fsl,imx93-cm33";
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clocks = <&clk IMX93_CLK_CM33_GATE>;
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status = "disabled";
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};
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soc@0 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x0 0x80000000>,
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<0x28000000 0x0 0x28000000 0x10000000>;
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aips1: bus@44000000 {
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compatible = "fsl,aips-bus", "simple-bus";
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reg = <0x44000000 0x800000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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aonmix_ns_gpr: syscon@44210000 {
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compatible = "fsl,imx93-aonmix-ns-syscfg", "syscon";
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reg = <0x44210000 0x1000>;
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};
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mu1: mailbox@44230000 {
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compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
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reg = <0x44230000 0x10000>;
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interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_MU1_B_GATE>;
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#mbox-cells = <2>;
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status = "disabled";
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};
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system_counter: timer@44290000 {
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compatible = "nxp,sysctr-timer";
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reg = <0x44290000 0x30000>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&osc_24m>;
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clock-names = "per";
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nxp,no-divider;
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};
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wdog1: watchdog@442d0000 {
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compatible = "fsl,imx93-wdt";
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reg = <0x442d0000 0x10000>;
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interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_WDOG1_GATE>;
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timeout-sec = <40>;
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status = "disabled";
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};
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wdog2: watchdog@442e0000 {
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compatible = "fsl,imx93-wdt";
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reg = <0x442e0000 0x10000>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_WDOG2_GATE>;
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timeout-sec = <40>;
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status = "disabled";
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};
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tpm1: pwm@44310000 {
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compatible = "fsl,imx7ulp-pwm";
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reg = <0x44310000 0x1000>;
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clocks = <&clk IMX93_CLK_TPM1_GATE>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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tpm2: pwm@44320000 {
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compatible = "fsl,imx7ulp-pwm";
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reg = <0x44320000 0x10000>;
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clocks = <&clk IMX93_CLK_TPM2_GATE>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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lpi2c1: i2c@44340000 {
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compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
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reg = <0x44340000 0x10000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_LPI2C1_GATE>,
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<&clk IMX93_CLK_BUS_AON>;
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clock-names = "per", "ipg";
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status = "disabled";
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};
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lpi2c2: i2c@44350000 {
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compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
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reg = <0x44350000 0x10000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_LPI2C2_GATE>,
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<&clk IMX93_CLK_BUS_AON>;
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clock-names = "per", "ipg";
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status = "disabled";
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};
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lpspi1: spi@44360000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
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reg = <0x44360000 0x10000>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_LPSPI1_GATE>,
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<&clk IMX93_CLK_BUS_AON>;
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clock-names = "per", "ipg";
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status = "disabled";
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};
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lpspi2: spi@44370000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
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reg = <0x44370000 0x10000>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_LPSPI2_GATE>,
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<&clk IMX93_CLK_BUS_AON>;
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clock-names = "per", "ipg";
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status = "disabled";
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};
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lpuart1: serial@44380000 {
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compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
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reg = <0x44380000 0x1000>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_LPUART1_GATE>;
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clock-names = "ipg";
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status = "disabled";
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};
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lpuart2: serial@44390000 {
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compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
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reg = <0x44390000 0x1000>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_LPUART2_GATE>;
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clock-names = "ipg";
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status = "disabled";
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};
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flexcan1: can@443a0000 {
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compatible = "fsl,imx93-flexcan";
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reg = <0x443a0000 0x10000>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_BUS_AON>,
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<&clk IMX93_CLK_CAN1_GATE>;
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clock-names = "ipg", "per";
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assigned-clocks = <&clk IMX93_CLK_CAN1>;
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assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
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assigned-clock-rates = <40000000>;
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fsl,clk-source = /bits/ 8 <0>;
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fsl,stop-mode = <&aonmix_ns_gpr 0x14 0>;
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status = "disabled";
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};
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iomuxc: pinctrl@443c0000 {
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compatible = "fsl,imx93-iomuxc";
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reg = <0x443c0000 0x10000>;
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status = "okay";
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};
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bbnsm: bbnsm@44440000 {
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compatible = "nxp,imx93-bbnsm", "syscon", "simple-mfd";
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reg = <0x44440000 0x10000>;
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bbnsm_rtc: rtc {
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compatible = "nxp,imx93-bbnsm-rtc";
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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};
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bbnsm_pwrkey: pwrkey {
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compatible = "nxp,imx93-bbnsm-pwrkey";
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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linux,code = <KEY_POWER>;
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};
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};
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clk: clock-controller@44450000 {
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compatible = "fsl,imx93-ccm";
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reg = <0x44450000 0x10000>;
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#clock-cells = <1>;
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clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>;
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clock-names = "osc_32k", "osc_24m", "clk_ext1";
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status = "okay";
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};
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src: system-controller@44460000 {
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compatible = "fsl,imx93-src", "syscon";
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reg = <0x44460000 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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mlmix: power-domain@44461800 {
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compatible = "fsl,imx93-src-slice";
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reg = <0x44461800 0x400>, <0x44464800 0x400>;
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#power-domain-cells = <0>;
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clocks = <&clk IMX93_CLK_ML_APB>,
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<&clk IMX93_CLK_ML>;
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};
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mediamix: power-domain@44462400 {
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compatible = "fsl,imx93-src-slice";
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reg = <0x44462400 0x400>, <0x44465800 0x400>;
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#power-domain-cells = <0>;
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clocks = <&clk IMX93_CLK_MEDIA_AXI>,
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<&clk IMX93_CLK_MEDIA_APB>;
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};
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};
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anatop: anatop@44480000 {
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compatible = "fsl,imx93-anatop", "syscon";
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reg = <0x44480000 0x2000>;
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};
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tmu: tmu@44482000 {
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compatible = "fsl,qoriq-tmu";
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reg = <0x44482000 0x1000>;
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clocks = <&clk IMX93_CLK_TMC_GATE>;
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little-endian;
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fsl,tmu-range = <0x800000da 0x800000e9
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0x80000102 0x8000012a
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0x80000166 0x800001a7
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0x800001b6>;
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fsl,tmu-calibration = <0x00000000 0x0000000e
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0x00000001 0x00000029
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0x00000002 0x00000056
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0x00000003 0x000000a2
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0x00000004 0x00000116
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0x00000005 0x00000195
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0x00000006 0x000001b2>;
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#thermal-sensor-cells = <1>;
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};
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adc1: adc@44530000 {
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compatible = "nxp,imx93-adc";
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reg = <0x44530000 0x10000>;
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interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_ADC1_GATE>;
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clock-names = "ipg";
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#io-channel-cells = <1>;
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status = "disabled";
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};
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};
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aips2: bus@42000000 {
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compatible = "fsl,aips-bus", "simple-bus";
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reg = <0x42000000 0x800000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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wakeupmix_gpr: syscon@42420000 {
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compatible = "fsl,imx93-wakeupmix-syscfg", "syscon";
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reg = <0x42420000 0x1000>;
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};
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mu2: mailbox@42440000 {
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compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
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reg = <0x42440000 0x10000>;
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interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_MU2_B_GATE>;
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#mbox-cells = <2>;
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status = "disabled";
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};
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wdog3: watchdog@42490000 {
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compatible = "fsl,imx93-wdt";
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reg = <0x42490000 0x10000>;
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_WDOG3_GATE>;
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timeout-sec = <40>;
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status = "disabled";
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};
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wdog4: watchdog@424a0000 {
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compatible = "fsl,imx93-wdt";
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reg = <0x424a0000 0x10000>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_WDOG4_GATE>;
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timeout-sec = <40>;
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status = "disabled";
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};
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wdog5: watchdog@424b0000 {
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compatible = "fsl,imx93-wdt";
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reg = <0x424b0000 0x10000>;
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_WDOG5_GATE>;
|
|
timeout-sec = <40>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tpm3: pwm@424e0000 {
|
|
compatible = "fsl,imx7ulp-pwm";
|
|
reg = <0x424e0000 0x1000>;
|
|
clocks = <&clk IMX93_CLK_TPM3_GATE>;
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tpm4: pwm@424f0000 {
|
|
compatible = "fsl,imx7ulp-pwm";
|
|
reg = <0x424f0000 0x10000>;
|
|
clocks = <&clk IMX93_CLK_TPM4_GATE>;
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tpm5: pwm@42500000 {
|
|
compatible = "fsl,imx7ulp-pwm";
|
|
reg = <0x42500000 0x10000>;
|
|
clocks = <&clk IMX93_CLK_TPM5_GATE>;
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tpm6: pwm@42510000 {
|
|
compatible = "fsl,imx7ulp-pwm";
|
|
reg = <0x42510000 0x10000>;
|
|
clocks = <&clk IMX93_CLK_TPM6_GATE>;
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
lpi2c3: i2c@42530000 {
|
|
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
|
|
reg = <0x42530000 0x10000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX93_CLK_LPI2C3_GATE>,
|
|
<&clk IMX93_CLK_BUS_WAKEUP>;
|
|
clock-names = "per", "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpi2c4: i2c@42540000 {
|
|
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
|
|
reg = <0x42540000 0x10000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX93_CLK_LPI2C4_GATE>,
|
|
<&clk IMX93_CLK_BUS_WAKEUP>;
|
|
clock-names = "per", "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpspi3: spi@42550000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
|
|
reg = <0x42550000 0x10000>;
|
|
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX93_CLK_LPSPI3_GATE>,
|
|
<&clk IMX93_CLK_BUS_WAKEUP>;
|
|
clock-names = "per", "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpspi4: spi@42560000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
|
|
reg = <0x42560000 0x10000>;
|
|
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX93_CLK_LPSPI4_GATE>,
|
|
<&clk IMX93_CLK_BUS_WAKEUP>;
|
|
clock-names = "per", "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpuart3: serial@42570000 {
|
|
compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
|
|
reg = <0x42570000 0x1000>;
|
|
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX93_CLK_LPUART3_GATE>;
|
|
clock-names = "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpuart4: serial@42580000 {
|
|
compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
|
|
reg = <0x42580000 0x1000>;
|
|
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX93_CLK_LPUART4_GATE>;
|
|
clock-names = "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpuart5: serial@42590000 {
|
|
compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
|
|
reg = <0x42590000 0x1000>;
|
|
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX93_CLK_LPUART5_GATE>;
|
|
clock-names = "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpuart6: serial@425a0000 {
|
|
compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
|
|
reg = <0x425a0000 0x1000>;
|
|
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX93_CLK_LPUART6_GATE>;
|
|
clock-names = "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
flexcan2: can@425b0000 {
|
|
compatible = "fsl,imx93-flexcan";
|
|
reg = <0x425b0000 0x10000>;
|
|
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
|
|
<&clk IMX93_CLK_CAN2_GATE>;
|
|
clock-names = "ipg", "per";
|
|
assigned-clocks = <&clk IMX93_CLK_CAN2>;
|
|
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
|
|
assigned-clock-rates = <40000000>;
|
|
fsl,clk-source = /bits/ 8 <0>;
|
|
fsl,stop-mode = <&wakeupmix_gpr 0x0c 2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
flexspi1: spi@425e0000 {
|
|
compatible = "nxp,imx8mm-fspi";
|
|
reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>;
|
|
reg-names = "fspi_base", "fspi_mmap";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX93_CLK_FLEXSPI1_GATE>,
|
|
<&clk IMX93_CLK_FLEXSPI1_GATE>;
|
|
clock-names = "fspi_en", "fspi";
|
|
assigned-clocks = <&clk IMX93_CLK_FLEXSPI1>;
|
|
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
lpuart7: serial@42690000 {
|
|
compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
|
|
reg = <0x42690000 0x1000>;
|
|
interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX93_CLK_LPUART7_GATE>;
|
|
clock-names = "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpuart8: serial@426a0000 {
|
|
compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
|
|
reg = <0x426a0000 0x1000>;
|
|
interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX93_CLK_LPUART8_GATE>;
|
|
clock-names = "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpi2c5: i2c@426b0000 {
|
|
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
|
|
reg = <0x426b0000 0x10000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX93_CLK_LPI2C5_GATE>,
|
|
<&clk IMX93_CLK_BUS_WAKEUP>;
|
|
clock-names = "per", "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpi2c6: i2c@426c0000 {
|
|
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
|
|
reg = <0x426c0000 0x10000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX93_CLK_LPI2C6_GATE>,
|
|
<&clk IMX93_CLK_BUS_WAKEUP>;
|
|
clock-names = "per", "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpi2c7: i2c@426d0000 {
|
|
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
|
|
reg = <0x426d0000 0x10000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX93_CLK_LPI2C7_GATE>,
|
|
<&clk IMX93_CLK_BUS_WAKEUP>;
|
|
clock-names = "per", "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpi2c8: i2c@426e0000 {
|
|
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
|
|
reg = <0x426e0000 0x10000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX93_CLK_LPI2C8_GATE>,
|
|
<&clk IMX93_CLK_BUS_WAKEUP>;
|
|
clock-names = "per", "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpspi5: spi@426f0000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
|
|
reg = <0x426f0000 0x10000>;
|
|
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX93_CLK_LPSPI5_GATE>,
|
|
<&clk IMX93_CLK_BUS_WAKEUP>;
|
|
clock-names = "per", "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpspi6: spi@42700000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
|
|
reg = <0x42700000 0x10000>;
|
|
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX93_CLK_LPSPI6_GATE>,
|
|
<&clk IMX93_CLK_BUS_WAKEUP>;
|
|
clock-names = "per", "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpspi7: spi@42710000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
|
|
reg = <0x42710000 0x10000>;
|
|
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX93_CLK_LPSPI7_GATE>,
|
|
<&clk IMX93_CLK_BUS_WAKEUP>;
|
|
clock-names = "per", "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpspi8: spi@42720000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
|
|
reg = <0x42720000 0x10000>;
|
|
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX93_CLK_LPSPI8_GATE>,
|
|
<&clk IMX93_CLK_BUS_WAKEUP>;
|
|
clock-names = "per", "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
};
|
|
|
|
aips3: bus@42800000 {
|
|
compatible = "fsl,aips-bus", "simple-bus";
|
|
reg = <0x42800000 0x800000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
usdhc1: mmc@42850000 {
|
|
compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
|
|
reg = <0x42850000 0x10000>;
|
|
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
|
|
<&clk IMX93_CLK_WAKEUP_AXI>,
|
|
<&clk IMX93_CLK_USDHC1_GATE>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
bus-width = <8>;
|
|
fsl,tuning-start-tap = <20>;
|
|
fsl,tuning-step = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usdhc2: mmc@42860000 {
|
|
compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
|
|
reg = <0x42860000 0x10000>;
|
|
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
|
|
<&clk IMX93_CLK_WAKEUP_AXI>,
|
|
<&clk IMX93_CLK_USDHC2_GATE>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
bus-width = <4>;
|
|
fsl,tuning-start-tap = <20>;
|
|
fsl,tuning-step = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
fec: ethernet@42890000 {
|
|
compatible = "fsl,imx93-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
|
|
reg = <0x42890000 0x10000>;
|
|
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX93_CLK_ENET1_GATE>,
|
|
<&clk IMX93_CLK_ENET1_GATE>,
|
|
<&clk IMX93_CLK_ENET_TIMER1>,
|
|
<&clk IMX93_CLK_ENET_REF>,
|
|
<&clk IMX93_CLK_ENET_REF_PHY>;
|
|
clock-names = "ipg", "ahb", "ptp",
|
|
"enet_clk_ref", "enet_out";
|
|
assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>,
|
|
<&clk IMX93_CLK_ENET_REF>,
|
|
<&clk IMX93_CLK_ENET_REF_PHY>;
|
|
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
|
|
<&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>,
|
|
<&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
|
|
assigned-clock-rates = <100000000>, <250000000>, <50000000>;
|
|
fsl,num-tx-queues = <3>;
|
|
fsl,num-rx-queues = <3>;
|
|
fsl,stop-mode = <&wakeupmix_gpr 0x0c 1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
eqos: ethernet@428a0000 {
|
|
compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a";
|
|
reg = <0x428a0000 0x10000>;
|
|
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "macirq", "eth_wake_irq";
|
|
clocks = <&clk IMX93_CLK_ENET_QOS_GATE>,
|
|
<&clk IMX93_CLK_ENET_QOS_GATE>,
|
|
<&clk IMX93_CLK_ENET_TIMER2>,
|
|
<&clk IMX93_CLK_ENET>,
|
|
<&clk IMX93_CLK_ENET_QOS_GATE>;
|
|
clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
|
|
assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>,
|
|
<&clk IMX93_CLK_ENET>;
|
|
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
|
|
<&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
|
|
assigned-clock-rates = <100000000>, <250000000>;
|
|
intf_mode = <&wakeupmix_gpr 0x28>;
|
|
snps,clk-csr = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usdhc3: mmc@428b0000 {
|
|
compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
|
|
reg = <0x428b0000 0x10000>;
|
|
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
|
|
<&clk IMX93_CLK_WAKEUP_AXI>,
|
|
<&clk IMX93_CLK_USDHC3_GATE>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
bus-width = <4>;
|
|
fsl,tuning-start-tap = <20>;
|
|
fsl,tuning-step = <2>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
gpio2: gpio@43810080 {
|
|
compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
|
|
reg = <0x43810080 0x1000>, <0x43810040 0x40>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&clk IMX93_CLK_GPIO2_GATE>,
|
|
<&clk IMX93_CLK_GPIO2_GATE>;
|
|
clock-names = "gpio", "port";
|
|
gpio-ranges = <&iomuxc 0 4 30>;
|
|
};
|
|
|
|
gpio3: gpio@43820080 {
|
|
compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
|
|
reg = <0x43820080 0x1000>, <0x43820040 0x40>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&clk IMX93_CLK_GPIO3_GATE>,
|
|
<&clk IMX93_CLK_GPIO3_GATE>;
|
|
clock-names = "gpio", "port";
|
|
gpio-ranges = <&iomuxc 0 84 8>, <&iomuxc 8 66 18>,
|
|
<&iomuxc 26 34 2>, <&iomuxc 28 0 4>;
|
|
};
|
|
|
|
gpio4: gpio@43830080 {
|
|
compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
|
|
reg = <0x43830080 0x1000>, <0x43830040 0x40>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&clk IMX93_CLK_GPIO4_GATE>,
|
|
<&clk IMX93_CLK_GPIO4_GATE>;
|
|
clock-names = "gpio", "port";
|
|
gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 36 2>;
|
|
};
|
|
|
|
gpio1: gpio@47400080 {
|
|
compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
|
|
reg = <0x47400080 0x1000>, <0x47400040 0x40>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&clk IMX93_CLK_GPIO1_GATE>,
|
|
<&clk IMX93_CLK_GPIO1_GATE>;
|
|
clock-names = "gpio", "port";
|
|
gpio-ranges = <&iomuxc 0 92 16>;
|
|
};
|
|
|
|
ocotp: efuse@47510000 {
|
|
compatible = "fsl,imx93-ocotp", "syscon";
|
|
reg = <0x47510000 0x10000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
};
|
|
|
|
s4muap: mailbox@47520000 {
|
|
compatible = "fsl,imx93-mu-s4";
|
|
reg = <0x47520000 0x10000>;
|
|
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "tx", "rx";
|
|
#mbox-cells = <2>;
|
|
};
|
|
|
|
media_blk_ctrl: system-controller@4ac10000 {
|
|
compatible = "fsl,imx93-media-blk-ctrl", "syscon";
|
|
reg = <0x4ac10000 0x10000>;
|
|
power-domains = <&mediamix>;
|
|
clocks = <&clk IMX93_CLK_MEDIA_APB>,
|
|
<&clk IMX93_CLK_MEDIA_AXI>,
|
|
<&clk IMX93_CLK_NIC_MEDIA_GATE>,
|
|
<&clk IMX93_CLK_MEDIA_DISP_PIX>,
|
|
<&clk IMX93_CLK_CAM_PIX>,
|
|
<&clk IMX93_CLK_PXP_GATE>,
|
|
<&clk IMX93_CLK_LCDIF_GATE>,
|
|
<&clk IMX93_CLK_ISI_GATE>,
|
|
<&clk IMX93_CLK_MIPI_CSI_GATE>,
|
|
<&clk IMX93_CLK_MIPI_DSI_GATE>;
|
|
clock-names = "apb", "axi", "nic", "disp", "cam",
|
|
"pxp", "lcdif", "isi", "csi", "dsi";
|
|
#power-domain-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ddr-pmu@4e300dc0 {
|
|
compatible = "fsl,imx93-ddr-pmu";
|
|
reg = <0x4e300dc0 0x200>;
|
|
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
};
|