Renesas fixes for v6.6 (take three)
- Sort out a few Kconfig dependency issues for the rich set of RISC-V
non-coherent DMA support.
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Merge tag 'renesas-fixes-for-v6.6-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/fixes
Renesas fixes for v6.6 (take three)
- Sort out a few Kconfig dependency issues for the rich set of RISC-V
non-coherent DMA support.
* tag 'renesas-fixes-for-v6.6-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
soc: renesas: ARCH_R9A07G043 depends on !RISCV_ISA_ZICBOM
riscv: only select DMA_DIRECT_REMAP from RISCV_ISA_ZICBOM and ERRATA_THEAD_PBMT
riscv: RISCV_NONSTANDARD_CACHE_OPS shouldn't depend on RISCV_DMA_NONCOHERENT
Link: https://lore.kernel.org/r/cover.1698312384.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
736a4aad8a
4 changed files with 4 additions and 3 deletions
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@ -273,11 +273,9 @@ config RISCV_DMA_NONCOHERENT
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select ARCH_HAS_SYNC_DMA_FOR_CPU
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select ARCH_HAS_SYNC_DMA_FOR_DEVICE
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select DMA_BOUNCE_UNALIGNED_KMALLOC if SWIOTLB
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select DMA_DIRECT_REMAP if MMU
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config RISCV_NONSTANDARD_CACHE_OPS
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bool
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depends on RISCV_DMA_NONCOHERENT
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help
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This enables function pointer support for non-standard noncoherent
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systems to handle cache management.
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@ -550,6 +548,7 @@ config RISCV_ISA_ZICBOM
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depends on RISCV_ALTERNATIVE
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default y
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select RISCV_DMA_NONCOHERENT
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select DMA_DIRECT_REMAP
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help
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Adds support to dynamically detect the presence of the ZICBOM
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extension (Cache Block Management Operations) and enable its
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@ -77,6 +77,7 @@ config ERRATA_THEAD_PBMT
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config ERRATA_THEAD_CMO
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bool "Apply T-Head cache management errata"
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depends on ERRATA_THEAD && MMU
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select DMA_DIRECT_REMAP
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select RISCV_DMA_NONCOHERENT
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default y
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help
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2
drivers/cache/Kconfig
vendored
2
drivers/cache/Kconfig
vendored
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@ -3,7 +3,7 @@ menu "Cache Drivers"
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config AX45MP_L2_CACHE
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bool "Andes Technology AX45MP L2 Cache controller"
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depends on RISCV_DMA_NONCOHERENT
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depends on RISCV
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select RISCV_NONSTANDARD_CACHE_OPS
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help
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Support for the L2 cache controller on Andes Technology AX45MP platforms.
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@ -335,6 +335,7 @@ config ARCH_R9A07G043
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bool "RISC-V Platform support for RZ/Five"
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depends on NONPORTABLE
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depends on RISCV_ALTERNATIVE
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depends on !RISCV_ISA_ZICBOM
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depends on RISCV_SBI
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select ARCH_RZG2L
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select AX45MP_L2_CACHE
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