Merge tag 'drm-misc-next-2023-04-06' of git://anongit.freedesktop.org/drm/drm-misc into drm-next
drm-misc-next for v6.4-rc1: UAPI Changes: Cross-subsystem Changes: - Document port and rotation dt bindings better. - For panel timing DT bindings, document that vsync and hsync are first, rather than last in image. - Fix video/aperture typos. Core Changes: - Reject prime DMA-Buf attachment if get_sg_table is missing. (For self-importing dma-buf only.) - Add prime import/export to vram-helper. - Fix oops in drm/vblank when init is not called. - Fixup xres/yres_virtual and other fixes in fb helper. - Improve SCDC debugs. - Skip setting deadline on modesets. - Assorted TTM fixes. Driver Changes: - Add lima usage stats. - Assorted fixes to bridge/lt8192b, tc358767, ivpu, bridge/ti-sn65dsi83, ps8640. - Use pci aperture helpers in drm/ast lynxfb, radeonfb. - Revert some lima patches, as they required a commit that has been reverted upstream. - Add AUO NE135FBM-N41 v8.1 eDP panel. - Add QAIC accel driver. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/64bb9696-a76a-89d9-1866-bcdf7c69c284@linux.intel.com
This commit is contained in:
Daniel Vetter
commit
52b113e968
51 changed files with 7004 additions and 231 deletions
397
include/uapi/drm/qaic_accel.h
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397
include/uapi/drm/qaic_accel.h
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/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
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*
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* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
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* Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef QAIC_ACCEL_H_
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#define QAIC_ACCEL_H_
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#include "drm.h"
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/* The length(4K) includes len and count fields of qaic_manage_msg */
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#define QAIC_MANAGE_MAX_MSG_LENGTH SZ_4K
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/* semaphore flags */
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#define QAIC_SEM_INSYNCFENCE 2
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#define QAIC_SEM_OUTSYNCFENCE 1
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/* Semaphore commands */
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#define QAIC_SEM_NOP 0
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#define QAIC_SEM_INIT 1
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#define QAIC_SEM_INC 2
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#define QAIC_SEM_DEC 3
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#define QAIC_SEM_WAIT_EQUAL 4
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#define QAIC_SEM_WAIT_GT_EQ 5 /* Greater than or equal */
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#define QAIC_SEM_WAIT_GT_0 6 /* Greater than 0 */
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#define QAIC_TRANS_UNDEFINED 0
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#define QAIC_TRANS_PASSTHROUGH_FROM_USR 1
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#define QAIC_TRANS_PASSTHROUGH_TO_USR 2
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#define QAIC_TRANS_PASSTHROUGH_FROM_DEV 3
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#define QAIC_TRANS_PASSTHROUGH_TO_DEV 4
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#define QAIC_TRANS_DMA_XFER_FROM_USR 5
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#define QAIC_TRANS_DMA_XFER_TO_DEV 6
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#define QAIC_TRANS_ACTIVATE_FROM_USR 7
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#define QAIC_TRANS_ACTIVATE_FROM_DEV 8
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#define QAIC_TRANS_ACTIVATE_TO_DEV 9
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#define QAIC_TRANS_DEACTIVATE_FROM_USR 10
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#define QAIC_TRANS_DEACTIVATE_FROM_DEV 11
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#define QAIC_TRANS_STATUS_FROM_USR 12
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#define QAIC_TRANS_STATUS_TO_USR 13
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#define QAIC_TRANS_STATUS_FROM_DEV 14
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#define QAIC_TRANS_STATUS_TO_DEV 15
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#define QAIC_TRANS_TERMINATE_FROM_DEV 16
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#define QAIC_TRANS_TERMINATE_TO_DEV 17
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#define QAIC_TRANS_DMA_XFER_CONT 18
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#define QAIC_TRANS_VALIDATE_PARTITION_FROM_DEV 19
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#define QAIC_TRANS_VALIDATE_PARTITION_TO_DEV 20
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/**
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* struct qaic_manage_trans_hdr - Header for a transaction in a manage message.
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* @type: In. Identifies this transaction. See QAIC_TRANS_* defines.
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* @len: In. Length of this transaction, including this header.
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*/
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struct qaic_manage_trans_hdr {
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__u32 type;
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__u32 len;
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};
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/**
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* struct qaic_manage_trans_passthrough - Defines a passthrough transaction.
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* @hdr: In. Header to identify this transaction.
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* @data: In. Payload of this ransaction. Opaque to the driver. Userspace must
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* encode in little endian and align/pad to 64-bit.
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*/
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struct qaic_manage_trans_passthrough {
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struct qaic_manage_trans_hdr hdr;
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__u8 data[];
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};
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/**
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* struct qaic_manage_trans_dma_xfer - Defines a DMA transfer transaction.
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* @hdr: In. Header to identify this transaction.
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* @tag: In. Identified this transfer in other transactions. Opaque to the
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* driver.
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* @pad: Structure padding.
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* @addr: In. Address of the data to DMA to the device.
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* @size: In. Length of the data to DMA to the device.
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*/
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struct qaic_manage_trans_dma_xfer {
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struct qaic_manage_trans_hdr hdr;
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__u32 tag;
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__u32 pad;
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__u64 addr;
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__u64 size;
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};
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/**
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* struct qaic_manage_trans_activate_to_dev - Defines an activate request.
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* @hdr: In. Header to identify this transaction.
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* @queue_size: In. Number of elements for DBC request and response queues.
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* @eventfd: Unused.
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* @options: In. Device specific options for this activate.
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* @pad: Structure padding. Must be 0.
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*/
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struct qaic_manage_trans_activate_to_dev {
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struct qaic_manage_trans_hdr hdr;
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__u32 queue_size;
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__u32 eventfd;
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__u32 options;
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__u32 pad;
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};
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/**
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* struct qaic_manage_trans_activate_from_dev - Defines an activate response.
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* @hdr: Out. Header to identify this transaction.
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* @status: Out. Return code of the request from the device.
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* @dbc_id: Out. Id of the assigned DBC for successful request.
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* @options: Out. Device specific options for this activate.
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*/
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struct qaic_manage_trans_activate_from_dev {
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struct qaic_manage_trans_hdr hdr;
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__u32 status;
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__u32 dbc_id;
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__u64 options;
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};
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/**
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* struct qaic_manage_trans_deactivate - Defines a deactivate request.
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* @hdr: In. Header to identify this transaction.
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* @dbc_id: In. Id of assigned DBC.
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* @pad: Structure padding. Must be 0.
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*/
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struct qaic_manage_trans_deactivate {
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struct qaic_manage_trans_hdr hdr;
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__u32 dbc_id;
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__u32 pad;
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};
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/**
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* struct qaic_manage_trans_status_to_dev - Defines a status request.
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* @hdr: In. Header to identify this transaction.
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*/
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struct qaic_manage_trans_status_to_dev {
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struct qaic_manage_trans_hdr hdr;
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};
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/**
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* struct qaic_manage_trans_status_from_dev - Defines a status response.
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* @hdr: Out. Header to identify this transaction.
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* @major: Out. NNC protocol version major number.
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* @minor: Out. NNC protocol version minor number.
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* @status: Out. Return code from device.
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* @status_flags: Out. Flags from device. Bit 0 indicates if CRCs are required.
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*/
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struct qaic_manage_trans_status_from_dev {
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struct qaic_manage_trans_hdr hdr;
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__u16 major;
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__u16 minor;
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__u32 status;
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__u64 status_flags;
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};
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/**
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* struct qaic_manage_msg - Defines a message to the device.
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* @len: In. Length of all the transactions contained within this message.
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* @count: In. Number of transactions in this message.
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* @data: In. Address to an array where the transactions can be found.
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*/
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struct qaic_manage_msg {
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__u32 len;
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__u32 count;
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__u64 data;
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};
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/**
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* struct qaic_create_bo - Defines a request to create a buffer object.
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* @size: In. Size of the buffer in bytes.
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* @handle: Out. GEM handle for the BO.
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* @pad: Structure padding. Must be 0.
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*/
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struct qaic_create_bo {
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__u64 size;
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__u32 handle;
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__u32 pad;
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};
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/**
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* struct qaic_mmap_bo - Defines a request to prepare a BO for mmap().
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* @handle: In. Handle of the GEM BO to prepare for mmap().
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* @pad: Structure padding. Must be 0.
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* @offset: Out. Offset value to provide to mmap().
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*/
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struct qaic_mmap_bo {
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__u32 handle;
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__u32 pad;
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__u64 offset;
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};
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/**
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* struct qaic_sem - Defines a semaphore command for a BO slice.
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* @val: In. Only lower 12 bits are valid.
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* @index: In. Only lower 5 bits are valid.
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* @presync: In. 1 if presync operation, 0 if postsync.
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* @cmd: In. One of QAIC_SEM_*.
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* @flags: In. Bitfield. See QAIC_SEM_INSYNCFENCE and QAIC_SEM_OUTSYNCFENCE
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* @pad: Structure padding. Must be 0.
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*/
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struct qaic_sem {
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__u16 val;
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__u8 index;
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__u8 presync;
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__u8 cmd;
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__u8 flags;
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__u16 pad;
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};
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/**
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* struct qaic_attach_slice_entry - Defines a single BO slice.
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* @size: In. Size of this slice in bytes.
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* @sem0: In. Semaphore command 0. Must be 0 is not valid.
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* @sem1: In. Semaphore command 1. Must be 0 is not valid.
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* @sem2: In. Semaphore command 2. Must be 0 is not valid.
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* @sem3: In. Semaphore command 3. Must be 0 is not valid.
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* @dev_addr: In. Device address this slice pushes to or pulls from.
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* @db_addr: In. Address of the doorbell to ring.
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* @db_data: In. Data to write to the doorbell.
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* @db_len: In. Size of the doorbell data in bits - 32, 16, or 8. 0 is for
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* inactive doorbells.
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* @offset: In. Start of this slice as an offset from the start of the BO.
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*/
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struct qaic_attach_slice_entry {
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__u64 size;
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struct qaic_sem sem0;
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struct qaic_sem sem1;
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struct qaic_sem sem2;
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struct qaic_sem sem3;
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__u64 dev_addr;
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__u64 db_addr;
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__u32 db_data;
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__u32 db_len;
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__u64 offset;
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};
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/**
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* struct qaic_attach_slice_hdr - Defines metadata for a set of BO slices.
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* @count: In. Number of slices for this BO.
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* @dbc_id: In. Associate the sliced BO with this DBC.
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* @handle: In. GEM handle of the BO to slice.
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* @dir: In. Direction of data flow. 1 = DMA_TO_DEVICE, 2 = DMA_FROM_DEVICE
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* @size: In. Total length of the BO.
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* If BO is imported (DMABUF/PRIME) then this size
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* should not exceed the size of DMABUF provided.
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* If BO is allocated using DRM_IOCTL_QAIC_CREATE_BO
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* then this size should be exactly same as the size
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* provided during DRM_IOCTL_QAIC_CREATE_BO.
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* @dev_addr: In. Device address this slice pushes to or pulls from.
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* @db_addr: In. Address of the doorbell to ring.
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* @db_data: In. Data to write to the doorbell.
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* @db_len: In. Size of the doorbell data in bits - 32, 16, or 8. 0 is for
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* inactive doorbells.
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* @offset: In. Start of this slice as an offset from the start of the BO.
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*/
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struct qaic_attach_slice_hdr {
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__u32 count;
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__u32 dbc_id;
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__u32 handle;
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__u32 dir;
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__u64 size;
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};
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/**
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* struct qaic_attach_slice - Defines a set of BO slices.
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* @hdr: In. Metadata of the set of slices.
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* @data: In. Pointer to an array containing the slice definitions.
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*/
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struct qaic_attach_slice {
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struct qaic_attach_slice_hdr hdr;
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__u64 data;
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};
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/**
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* struct qaic_execute_entry - Defines a BO to submit to the device.
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* @handle: In. GEM handle of the BO to commit to the device.
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* @dir: In. Direction of data. 1 = to device, 2 = from device.
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*/
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struct qaic_execute_entry {
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__u32 handle;
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__u32 dir;
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};
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/**
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* struct qaic_partial_execute_entry - Defines a BO to resize and submit.
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* @handle: In. GEM handle of the BO to commit to the device.
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* @dir: In. Direction of data. 1 = to device, 2 = from device.
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* @resize: In. New size of the BO. Must be <= the original BO size. 0 is
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* short for no resize.
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*/
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struct qaic_partial_execute_entry {
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__u32 handle;
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__u32 dir;
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__u64 resize;
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};
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/**
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* struct qaic_execute_hdr - Defines metadata for BO submission.
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* @count: In. Number of BOs to submit.
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* @dbc_id: In. DBC to submit the BOs on.
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*/
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struct qaic_execute_hdr {
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__u32 count;
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__u32 dbc_id;
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};
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/**
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* struct qaic_execute - Defines a list of BOs to submit to the device.
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* @hdr: In. BO list metadata.
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* @data: In. Pointer to an array of BOs to submit.
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*/
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struct qaic_execute {
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struct qaic_execute_hdr hdr;
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__u64 data;
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};
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/**
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* struct qaic_wait - Defines a blocking wait for BO execution.
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* @handle: In. GEM handle of the BO to wait on.
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* @timeout: In. Maximum time in ms to wait for the BO.
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* @dbc_id: In. DBC the BO is submitted to.
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* @pad: Structure padding. Must be 0.
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*/
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struct qaic_wait {
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__u32 handle;
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__u32 timeout;
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__u32 dbc_id;
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__u32 pad;
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};
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/**
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* struct qaic_perf_stats_hdr - Defines metadata for getting BO perf info.
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* @count: In. Number of BOs requested.
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* @pad: Structure padding. Must be 0.
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* @dbc_id: In. DBC the BO are associated with.
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*/
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struct qaic_perf_stats_hdr {
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__u16 count;
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__u16 pad;
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__u32 dbc_id;
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};
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/**
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* struct qaic_perf_stats - Defines a request for getting BO perf info.
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* @hdr: In. Request metadata
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* @data: In. Pointer to array of stats structures that will receive the data.
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*/
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struct qaic_perf_stats {
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struct qaic_perf_stats_hdr hdr;
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__u64 data;
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};
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/**
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* struct qaic_perf_stats_entry - Defines a BO perf info.
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* @handle: In. GEM handle of the BO to get perf stats for.
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* @queue_level_before: Out. Number of elements in the queue before this BO
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* was submitted.
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* @num_queue_element: Out. Number of elements added to the queue to submit
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* this BO.
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* @submit_latency_us: Out. Time taken by the driver to submit this BO.
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* @device_latency_us: Out. Time taken by the device to execute this BO.
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* @pad: Structure padding. Must be 0.
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*/
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struct qaic_perf_stats_entry {
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__u32 handle;
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__u32 queue_level_before;
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__u32 num_queue_element;
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__u32 submit_latency_us;
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__u32 device_latency_us;
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__u32 pad;
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};
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#define DRM_QAIC_MANAGE 0x00
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#define DRM_QAIC_CREATE_BO 0x01
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#define DRM_QAIC_MMAP_BO 0x02
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#define DRM_QAIC_ATTACH_SLICE_BO 0x03
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#define DRM_QAIC_EXECUTE_BO 0x04
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#define DRM_QAIC_PARTIAL_EXECUTE_BO 0x05
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#define DRM_QAIC_WAIT_BO 0x06
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#define DRM_QAIC_PERF_STATS_BO 0x07
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#define DRM_IOCTL_QAIC_MANAGE DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_MANAGE, struct qaic_manage_msg)
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#define DRM_IOCTL_QAIC_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_CREATE_BO, struct qaic_create_bo)
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#define DRM_IOCTL_QAIC_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_MMAP_BO, struct qaic_mmap_bo)
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#define DRM_IOCTL_QAIC_ATTACH_SLICE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_ATTACH_SLICE_BO, struct qaic_attach_slice)
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#define DRM_IOCTL_QAIC_EXECUTE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_EXECUTE_BO, struct qaic_execute)
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#define DRM_IOCTL_QAIC_PARTIAL_EXECUTE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_PARTIAL_EXECUTE_BO, struct qaic_execute)
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#define DRM_IOCTL_QAIC_WAIT_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_WAIT_BO, struct qaic_wait)
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#define DRM_IOCTL_QAIC_PERF_STATS_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_PERF_STATS_BO, struct qaic_perf_stats)
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#if defined(__cplusplus)
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}
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#endif
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#endif /* QAIC_ACCEL_H_ */
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