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Qualcomm driver updates for v5.18

Browse source 
This refactors the Qualcomm mdt file loader, to partially decouple it
 from the SCM peripheral-authentication-service. This is needed as newer
 platforms, such as the Qualcomm SM8450, require the metadata to remain
 accessible to TrustZone during a longer time. This is followed by the
 introduction of remoteproc drivers for SM8450 (Snapdragon 8 Gen 1).
 
 It changes the way hardware version differences are handled in the LLCC
 driver and introduces support for Qualcomm SM8450. While updating the dt
 binding for LLCC it also introduces the missing SM8350 compatible.
 
 The ocmem and aoss drivers gains missing put_device() calls and rpmpd
 gains a missing check for kcalloc() failure.
 
 The SPM driver is updated to avoid instantiating the SPM cpuidle devices
 if the CPUs aren't controlled by SPM, such as when Snapdragon 8916
 operates in 32-bit mode without PSCI.
 
 The RPM power-domain driver gains MSM8226 support.
 
 Lastly the socinfo driver gains knowledge about a few new SoCs and
 PMICs.
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Merge tag 'qcom-drivers-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/drivers

Qualcomm driver updates for v5.18

This refactors the Qualcomm mdt file loader, to partially decouple it
from the SCM peripheral-authentication-service. This is needed as newer
platforms, such as the Qualcomm SM8450, require the metadata to remain
accessible to TrustZone during a longer time. This is followed by the
introduction of remoteproc drivers for SM8450 (Snapdragon 8 Gen 1).

It changes the way hardware version differences are handled in the LLCC
driver and introduces support for Qualcomm SM8450. While updating the dt
binding for LLCC it also introduces the missing SM8350 compatible.

The ocmem and aoss drivers gains missing put_device() calls and rpmpd
gains a missing check for kcalloc() failure.

The SPM driver is updated to avoid instantiating the SPM cpuidle devices
if the CPUs aren't controlled by SPM, such as when Snapdragon 8916
operates in 32-bit mode without PSCI.

The RPM power-domain driver gains MSM8226 support.

Lastly the socinfo driver gains knowledge about a few new SoCs and
PMICs.

* tag 'qcom-drivers-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (37 commits)
  soc: qcom: rpmpd: Add MSM8226 support
  dt-bindings: power: rpmpd: Add MSM8226 to rpmpd binding
  soc: qcom: mdt_loader: Fix split-firmware condition
  dt-bindings: arm: msm: Add LLCC compatible for SM8450
  dt-bindings: arm: msm: Add LLCC compatible for SM8350
  soc: qcom: llcc: Add configuration data for SM8450 SoC
  soc: qcom: llcc: Update register offsets for newer LLCC HW
  soc: qcom: llcc: Add missing llcc configuration data
  soc: qcom: llcc: Add write-cache cacheable support
  soc: qcom: llcc: Update the logic for version info extraction
  soc: qcom: llcc: Add support for 16 ways of allocation
  soc: qcom: socinfo: Add some more PMICs and SoCs
  firmware: qcom: scm: Add support for MC boot address API
  firmware: qcom: scm: Drop cpumask parameter from set_boot_addr()
  firmware: qcom: scm: Simplify set_cold/warm_boot_addr()
  cpuidle: qcom-spm: Check if any CPU is managed by SPM
  remoteproc: qcom: pas: Add SM8450 remoteproc support
  dt-bindings: remoteproc: qcom: pas: Add SM8450 PAS compatibles
  remoteproc: qcom: pas: Carry PAS metadata context
  soc: qcom: mdt_loader: Extract PAS operations
  ...

Link: https://lore.kernel.org/r/20220301042055.1804859-1-bjorn.andersson@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2022-03-01 19:24:20 +01:00
commit 4d558d4d88
20 changed files with 537 additions and 224 deletions
Download patch file Download diff file Expand all files Collapse all files

16
include/linux/qcom_scm.h
View file

@ -63,13 +63,21 @@ enum qcom_scm_ice_cipher {
extern bool qcom_scm_is_available(void);
extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
extern int qcom_scm_set_cold_boot_addr(void *entry);
extern int qcom_scm_set_warm_boot_addr(void *entry);
extern void qcom_scm_cpu_power_down(u32 flags);
extern int qcom_scm_set_remote_state(u32 state, u32 id);
struct qcom_scm_pas_metadata {
void *ptr;
dma_addr_t phys;
ssize_t size;
};
extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
size_t size);
size_t size,
struct qcom_scm_pas_metadata *ctx);
void qcom_scm_pas_metadata_release(struct qcom_scm_pas_metadata *ctx);
extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
phys_addr_t size);
extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
@ -83,6 +91,7 @@ extern bool qcom_scm_restore_sec_cfg_available(void);
extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
extern int qcom_scm_iommu_set_cp_pool_size(u32 spare, u32 size);
extern int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size,
u32 cp_nonpixel_start,
u32 cp_nonpixel_size);
@ -107,6 +116,7 @@ extern bool qcom_scm_hdcp_available(void);
extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
u32 *resp);
extern int qcom_scm_iommu_set_pt_format(u32 sec_id, u32 ctx_num, u32 pt_fmt);
extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en);
extern int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val,

9
include/linux/soc/qcom/llcc-qcom.h
View file

@ -35,7 +35,12 @@
#define LLCC_WRCACHE 31
#define LLCC_CVPFW 32
#define LLCC_CPUSS1 33
#define LLCC_CAMEXP0 34
#define LLCC_CPUMTE 35
#define LLCC_CPUHWT 36
#define LLCC_MDMCLAD2 37
#define LLCC_CAMEXP1 38
#define LLCC_AENPU 45
/**
* struct llcc_slice_desc - Cache slice descriptor
@ -83,7 +88,7 @@ struct llcc_edac_reg_data {
* @bitmap: Bit map to track the active slice ids
* @offsets: Pointer to the bank offsets array
* @ecc_irq: interrupt for llcc cache error detection and reporting
* @major_version: Indicates the LLCC major version
* @version: Indicates the LLCC version
*/
struct llcc_drv_data {
struct regmap *regmap;
@ -96,7 +101,7 @@ struct llcc_drv_data {
unsigned long *bitmap;
u32 *offsets;
int ecc_irq;
u32 major_version;
u32 version;
};
#if IS_ENABLED(CONFIG_QCOM_LLCC)

17
include/linux/soc/qcom/mdt_loader.h
View file

@ -10,10 +10,14 @@
struct device;
struct firmware;
struct qcom_scm_pas_metadata;
#if IS_ENABLED(CONFIG_QCOM_MDT_LOADER)
ssize_t qcom_mdt_get_size(const struct firmware *fw);
int qcom_mdt_pas_init(struct device *dev, const struct firmware *fw,
const char *fw_name, int pas_id, phys_addr_t mem_phys,
struct qcom_scm_pas_metadata *pas_metadata_ctx);
int qcom_mdt_load(struct device *dev, const struct firmware *fw,
const char *fw_name, int pas_id, void *mem_region,
phys_addr_t mem_phys, size_t mem_size,
@ -23,7 +27,8 @@ int qcom_mdt_load_no_init(struct device *dev, const struct firmware *fw,
const char *fw_name, int pas_id, void *mem_region,
phys_addr_t mem_phys, size_t mem_size,
phys_addr_t *reloc_base);
void *qcom_mdt_read_metadata(const struct firmware *fw, size_t *data_len);
void *qcom_mdt_read_metadata(const struct firmware *fw, size_t *data_len,
const char *fw_name, struct device *dev);
#else /* !IS_ENABLED(CONFIG_QCOM_MDT_LOADER) */
@ -32,6 +37,13 @@ static inline ssize_t qcom_mdt_get_size(const struct firmware *fw)
return -ENODEV;
}
static inline int qcom_mdt_pas_init(struct device *dev, const struct firmware *fw,
const char *fw_name, int pas_id, phys_addr_t mem_phys,
struct qcom_scm_pas_metadata *pas_metadata_ctx)
{
return -ENODEV;
}
static inline int qcom_mdt_load(struct device *dev, const struct firmware *fw,
const char *fw_name, int pas_id,
void *mem_region, phys_addr_t mem_phys,
@ -51,7 +63,8 @@ static inline int qcom_mdt_load_no_init(struct device *dev,
}
static inline void *qcom_mdt_read_metadata(const struct firmware *fw,
size_t *data_len)
size_t *data_len, const char *fw_name,
struct device *dev)
{
return ERR_PTR(-ENODEV);
}