dpll: spec: Add Netlink spec in YAML
Add a protocol spec for DPLL. Add code generated from the spec. Signed-off-by: Jakub Kicinski <kuba@kernel.org> Signed-off-by: Michal Michalik <michal.michalik@intel.com> Signed-off-by: Vadim Fedorenko <vadim.fedorenko@linux.dev> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com> Signed-off-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Vadim Fedorenko
David S. Miller
parent
dbb291f193
commit
3badff3a25
4 changed files with 902 additions and 0 deletions
201
include/uapi/linux/dpll.h
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include/uapi/linux/dpll.h
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/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
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/* Do not edit directly, auto-generated from: */
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/* Documentation/netlink/specs/dpll.yaml */
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/* YNL-GEN uapi header */
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#ifndef _UAPI_LINUX_DPLL_H
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#define _UAPI_LINUX_DPLL_H
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#define DPLL_FAMILY_NAME "dpll"
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#define DPLL_FAMILY_VERSION 1
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/**
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* enum dpll_mode - working modes a dpll can support, differentiates if and how
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* dpll selects one of its inputs to syntonize with it, valid values for
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* DPLL_A_MODE attribute
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* @DPLL_MODE_MANUAL: input can be only selected by sending a request to dpll
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* @DPLL_MODE_AUTOMATIC: highest prio input pin auto selected by dpll
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*/
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enum dpll_mode {
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DPLL_MODE_MANUAL = 1,
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DPLL_MODE_AUTOMATIC,
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/* private: */
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__DPLL_MODE_MAX,
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DPLL_MODE_MAX = (__DPLL_MODE_MAX - 1)
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};
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/**
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* enum dpll_lock_status - provides information of dpll device lock status,
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* valid values for DPLL_A_LOCK_STATUS attribute
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* @DPLL_LOCK_STATUS_UNLOCKED: dpll was not yet locked to any valid input (or
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* forced by setting DPLL_A_MODE to DPLL_MODE_DETACHED)
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* @DPLL_LOCK_STATUS_LOCKED: dpll is locked to a valid signal, but no holdover
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* available
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* @DPLL_LOCK_STATUS_LOCKED_HO_ACQ: dpll is locked and holdover acquired
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* @DPLL_LOCK_STATUS_HOLDOVER: dpll is in holdover state - lost a valid lock or
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* was forced by disconnecting all the pins (latter possible only when dpll
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* lock-state was already DPLL_LOCK_STATUS_LOCKED_HO_ACQ, if dpll lock-state
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* was not DPLL_LOCK_STATUS_LOCKED_HO_ACQ, the dpll's lock-state shall remain
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* DPLL_LOCK_STATUS_UNLOCKED)
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*/
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enum dpll_lock_status {
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DPLL_LOCK_STATUS_UNLOCKED = 1,
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DPLL_LOCK_STATUS_LOCKED,
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DPLL_LOCK_STATUS_LOCKED_HO_ACQ,
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DPLL_LOCK_STATUS_HOLDOVER,
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/* private: */
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__DPLL_LOCK_STATUS_MAX,
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DPLL_LOCK_STATUS_MAX = (__DPLL_LOCK_STATUS_MAX - 1)
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};
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#define DPLL_TEMP_DIVIDER 1000
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/**
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* enum dpll_type - type of dpll, valid values for DPLL_A_TYPE attribute
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* @DPLL_TYPE_PPS: dpll produces Pulse-Per-Second signal
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* @DPLL_TYPE_EEC: dpll drives the Ethernet Equipment Clock
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*/
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enum dpll_type {
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DPLL_TYPE_PPS = 1,
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DPLL_TYPE_EEC,
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/* private: */
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__DPLL_TYPE_MAX,
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DPLL_TYPE_MAX = (__DPLL_TYPE_MAX - 1)
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};
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/**
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* enum dpll_pin_type - defines possible types of a pin, valid values for
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* DPLL_A_PIN_TYPE attribute
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* @DPLL_PIN_TYPE_MUX: aggregates another layer of selectable pins
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* @DPLL_PIN_TYPE_EXT: external input
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* @DPLL_PIN_TYPE_SYNCE_ETH_PORT: ethernet port PHY's recovered clock
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* @DPLL_PIN_TYPE_INT_OSCILLATOR: device internal oscillator
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* @DPLL_PIN_TYPE_GNSS: GNSS recovered clock
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*/
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enum dpll_pin_type {
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DPLL_PIN_TYPE_MUX = 1,
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DPLL_PIN_TYPE_EXT,
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DPLL_PIN_TYPE_SYNCE_ETH_PORT,
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DPLL_PIN_TYPE_INT_OSCILLATOR,
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DPLL_PIN_TYPE_GNSS,
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/* private: */
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__DPLL_PIN_TYPE_MAX,
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DPLL_PIN_TYPE_MAX = (__DPLL_PIN_TYPE_MAX - 1)
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};
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/**
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* enum dpll_pin_direction - defines possible direction of a pin, valid values
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* for DPLL_A_PIN_DIRECTION attribute
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* @DPLL_PIN_DIRECTION_INPUT: pin used as a input of a signal
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* @DPLL_PIN_DIRECTION_OUTPUT: pin used to output the signal
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*/
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enum dpll_pin_direction {
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DPLL_PIN_DIRECTION_INPUT = 1,
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DPLL_PIN_DIRECTION_OUTPUT,
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/* private: */
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__DPLL_PIN_DIRECTION_MAX,
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DPLL_PIN_DIRECTION_MAX = (__DPLL_PIN_DIRECTION_MAX - 1)
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};
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#define DPLL_PIN_FREQUENCY_1_HZ 1
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#define DPLL_PIN_FREQUENCY_10_KHZ 10000
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#define DPLL_PIN_FREQUENCY_77_5_KHZ 77500
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#define DPLL_PIN_FREQUENCY_10_MHZ 10000000
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/**
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* enum dpll_pin_state - defines possible states of a pin, valid values for
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* DPLL_A_PIN_STATE attribute
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* @DPLL_PIN_STATE_CONNECTED: pin connected, active input of phase locked loop
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* @DPLL_PIN_STATE_DISCONNECTED: pin disconnected, not considered as a valid
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* input
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* @DPLL_PIN_STATE_SELECTABLE: pin enabled for automatic input selection
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*/
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enum dpll_pin_state {
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DPLL_PIN_STATE_CONNECTED = 1,
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DPLL_PIN_STATE_DISCONNECTED,
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DPLL_PIN_STATE_SELECTABLE,
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/* private: */
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__DPLL_PIN_STATE_MAX,
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DPLL_PIN_STATE_MAX = (__DPLL_PIN_STATE_MAX - 1)
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};
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/**
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* enum dpll_pin_capabilities - defines possible capabilities of a pin, valid
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* flags on DPLL_A_PIN_CAPABILITIES attribute
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* @DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE: pin direction can be changed
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* @DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE: pin priority can be changed
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* @DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE: pin state can be changed
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*/
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enum dpll_pin_capabilities {
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DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE = 1,
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DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE = 2,
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DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE = 4,
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};
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enum dpll_a {
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DPLL_A_ID = 1,
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DPLL_A_MODULE_NAME,
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DPLL_A_PAD,
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DPLL_A_CLOCK_ID,
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DPLL_A_MODE,
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DPLL_A_MODE_SUPPORTED,
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DPLL_A_LOCK_STATUS,
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DPLL_A_TEMP,
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DPLL_A_TYPE,
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__DPLL_A_MAX,
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DPLL_A_MAX = (__DPLL_A_MAX - 1)
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};
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enum dpll_a_pin {
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DPLL_A_PIN_ID = 1,
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DPLL_A_PIN_PARENT_ID,
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DPLL_A_PIN_MODULE_NAME,
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DPLL_A_PIN_PAD,
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DPLL_A_PIN_CLOCK_ID,
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DPLL_A_PIN_BOARD_LABEL,
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DPLL_A_PIN_PANEL_LABEL,
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DPLL_A_PIN_PACKAGE_LABEL,
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DPLL_A_PIN_TYPE,
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DPLL_A_PIN_DIRECTION,
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DPLL_A_PIN_FREQUENCY,
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DPLL_A_PIN_FREQUENCY_SUPPORTED,
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DPLL_A_PIN_FREQUENCY_MIN,
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DPLL_A_PIN_FREQUENCY_MAX,
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DPLL_A_PIN_PRIO,
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DPLL_A_PIN_STATE,
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DPLL_A_PIN_CAPABILITIES,
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DPLL_A_PIN_PARENT_DEVICE,
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DPLL_A_PIN_PARENT_PIN,
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__DPLL_A_PIN_MAX,
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DPLL_A_PIN_MAX = (__DPLL_A_PIN_MAX - 1)
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};
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enum dpll_cmd {
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DPLL_CMD_DEVICE_ID_GET = 1,
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DPLL_CMD_DEVICE_GET,
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DPLL_CMD_DEVICE_SET,
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DPLL_CMD_DEVICE_CREATE_NTF,
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DPLL_CMD_DEVICE_DELETE_NTF,
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DPLL_CMD_DEVICE_CHANGE_NTF,
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DPLL_CMD_PIN_ID_GET,
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DPLL_CMD_PIN_GET,
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DPLL_CMD_PIN_SET,
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DPLL_CMD_PIN_CREATE_NTF,
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DPLL_CMD_PIN_DELETE_NTF,
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DPLL_CMD_PIN_CHANGE_NTF,
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__DPLL_CMD_MAX,
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DPLL_CMD_MAX = (__DPLL_CMD_MAX - 1)
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};
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#define DPLL_MCGRP_MONITOR "monitor"
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#endif /* _UAPI_LINUX_DPLL_H */
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