Qualcomm driver updates for v5.6
* SCM major refactoring and cleanup * Properly flag active only power domains as active only * Add SC7180 and SM8150 RPMH power domains * Return EPROBE_DEFER from QMI if packet family is not yet available -----BEGIN PGP SIGNATURE----- iQJPBAABCAA5FiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAl4czaUbHGJqb3JuLmFu ZGVyc3NvbkBsaW5hcm8ub3JnAAoJEAsfOT8Nma3FgKkP/1QC1e9VUQ5xc25A+2g0 5fVbOUkQxHLsPtTuN2GUwlxo5dj/dTnvXrQziQLfSGeAhX8FRNnImH0NCwNt7vmU i8XeRV/+Biv5IXhdM5k7IgT5bIwj3cQbzfswUL9KcCBxceJs8WDhtiu2MxeZh1g2 Gjq5+pRpC8yOC3v8AiFDWINoBduBqJGwucBtIE33/+29RqN4b7hLl4WK75yvp2Ce mpnB0Pl7GcvVeQZNAogUQW1u7kogmq+ByqBhpYXhlhUGw/CYSF2gIdfU6piiEJCz GWYfslABgYcGJGwMu+1RGVxe5+5I21ONUj2t8ichS5kmIZQ1lnavEAeGJ6cM8G3Y kDsQSE5eTfFJ13lX0HXCd6COUS6ZBV0xcoUek+gvzIu94U9l2D/qINf9kX91cPFq OSJlFJG1Yx9rcL1j1ROhDMMvuzr9QYslZZyGTRwVIwXLMQRT3Xzpx4qzATgWme5H vPJ55dMtxAWPk5NqxHurFbDP5nIRPyJ1M7IgjTJQrWp97mXx3+RCKdO6UEeqJu/1 wdp7IwziErNjOAbFgdboFdncFOEvwctwayDOEjb7gZE8WsSCa1LwXWZfXulkaOcC MTYnLZKZJtRJiy8WT/NvIukc60CnjYMj6IV1Vkem6NGSkvglhpRCGrxUuKi76+JR 5vPfeYhJ79KlkTWSr8lhh5VG =IcVk -----END PGP SIGNATURE----- Merge tag 'qcom-drivers-for-5.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/drivers Qualcomm driver updates for v5.6 * SCM major refactoring and cleanup * Properly flag active only power domains as active only * Add SC7180 and SM8150 RPMH power domains * Return EPROBE_DEFER from QMI if packet family is not yet available * tag 'qcom-drivers-for-5.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (27 commits) firmware: qcom_scm: Dynamically support SMCCC and legacy conventions firmware: qcom_scm: Remove thin wrappers firmware: qcom_scm: Order functions, definitions by service/command firmware: qcom_scm-32: Add device argument to atomic calls firmware: qcom_scm-32: Create common legacy atomic call firmware: qcom_scm-32: Move SMCCC register filling to qcom_scm_call firmware: qcom_scm-32: Use qcom_scm_desc in non-atomic calls firmware: qcom_scm-32: Add funcnum IDs firmware: qcom_scm-32: Use SMC arch wrappers firmware: qcom_scm-64: Improve SMC convention detection firmware: qcom_scm-64: Move SMC register filling to qcom_scm_call_smccc firmware: qcom_scm-64: Add SCM results struct firmware: qcom_scm-64: Move svc/cmd/owner into qcom_scm_desc firmware: qcom_scm-64: Make SMC macros less magical firmware: qcom_scm: Remove unused qcom_scm_get_version firmware: qcom_scm: Apply consistent naming scheme to command IDs firmware: qcom_scm: Rename macros and structures soc: qcom: rpmhpd: Set 'active_only' for active only power domains firmware: scm: Add stubs for OCMEM and restore_sec_cfg_available dt-bindings: power: rpmpd: Convert rpmpd bindings to yaml ... Link: https://lore.kernel.org/r/20200113204405.GD3325@yoga Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
333505a406
16 changed files with 1515 additions and 1752 deletions
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@ -1,5 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (c) 2010-2015, 2018, The Linux Foundation. All rights reserved.
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/* Copyright (c) 2010-2015, 2018-2019 The Linux Foundation. All rights reserved.
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* Copyright (C) 2015 Linaro Ltd.
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*/
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#ifndef __QCOM_SCM_H
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@ -55,77 +55,94 @@ enum qcom_scm_sec_dev_id {
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#define QCOM_SCM_PERM_RWX (QCOM_SCM_PERM_RW | QCOM_SCM_PERM_EXEC)
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#if IS_ENABLED(CONFIG_QCOM_SCM)
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extern bool qcom_scm_is_available(void);
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extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
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extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
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extern bool qcom_scm_is_available(void);
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extern bool qcom_scm_hdcp_available(void);
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extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
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u32 *resp);
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extern bool qcom_scm_ocmem_lock_available(void);
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extern int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset,
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u32 size, u32 mode);
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extern int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset,
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u32 size);
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extern bool qcom_scm_pas_supported(u32 peripheral);
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extern void qcom_scm_cpu_power_down(u32 flags);
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extern int qcom_scm_set_remote_state(u32 state, u32 id);
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extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
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size_t size);
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extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
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phys_addr_t size);
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extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
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extern int qcom_scm_pas_shutdown(u32 peripheral);
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extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
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unsigned int *src,
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const struct qcom_scm_vmperm *newvm,
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unsigned int dest_cnt);
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extern void qcom_scm_cpu_power_down(u32 flags);
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extern u32 qcom_scm_get_version(void);
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extern int qcom_scm_set_remote_state(u32 state, u32 id);
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extern bool qcom_scm_pas_supported(u32 peripheral);
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extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
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extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
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extern bool qcom_scm_restore_sec_cfg_available(void);
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extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
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extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
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extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
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extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
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unsigned int *src,
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const struct qcom_scm_vmperm *newvm,
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unsigned int dest_cnt);
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extern bool qcom_scm_ocmem_lock_available(void);
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extern int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset,
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u32 size, u32 mode);
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extern int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset,
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u32 size);
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extern bool qcom_scm_hdcp_available(void);
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extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
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u32 *resp);
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extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en);
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extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
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extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
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#else
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#include <linux/errno.h>
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static inline
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int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
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{
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return -ENODEV;
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}
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static inline
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int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
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{
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return -ENODEV;
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}
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static inline bool qcom_scm_is_available(void) { return false; }
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static inline int qcom_scm_set_cold_boot_addr(void *entry,
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const cpumask_t *cpus) { return -ENODEV; }
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static inline int qcom_scm_set_warm_boot_addr(void *entry,
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const cpumask_t *cpus) { return -ENODEV; }
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static inline void qcom_scm_cpu_power_down(u32 flags) {}
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static inline u32 qcom_scm_set_remote_state(u32 state,u32 id)
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{ return -ENODEV; }
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static inline int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
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size_t size) { return -ENODEV; }
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static inline int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
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phys_addr_t size) { return -ENODEV; }
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static inline int qcom_scm_pas_auth_and_reset(u32 peripheral)
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{ return -ENODEV; }
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static inline int qcom_scm_pas_shutdown(u32 peripheral) { return -ENODEV; }
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static inline bool qcom_scm_pas_supported(u32 peripheral) { return false; }
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static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val)
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{ return -ENODEV; }
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static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val)
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{ return -ENODEV; }
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static inline bool qcom_scm_restore_sec_cfg_available(void) { return false; }
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static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare)
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{ return -ENODEV; }
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static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size)
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{ return -ENODEV; }
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static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare)
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{ return -ENODEV; }
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static inline int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
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unsigned int *src, const struct qcom_scm_vmperm *newvm,
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unsigned int dest_cnt) { return -ENODEV; }
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static inline bool qcom_scm_ocmem_lock_available(void) { return false; }
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static inline int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset,
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u32 size, u32 mode) { return -ENODEV; }
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static inline int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id,
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u32 offset, u32 size) { return -ENODEV; }
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static inline bool qcom_scm_hdcp_available(void) { return false; }
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static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
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u32 *resp) { return -ENODEV; }
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static inline bool qcom_scm_pas_supported(u32 peripheral) { return false; }
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static inline int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
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size_t size) { return -ENODEV; }
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static inline int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
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phys_addr_t size) { return -ENODEV; }
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static inline int
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qcom_scm_pas_auth_and_reset(u32 peripheral) { return -ENODEV; }
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static inline int qcom_scm_pas_shutdown(u32 peripheral) { return -ENODEV; }
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static inline int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
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unsigned int *src,
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const struct qcom_scm_vmperm *newvm,
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unsigned int dest_cnt) { return -ENODEV; }
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static inline void qcom_scm_cpu_power_down(u32 flags) {}
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static inline u32 qcom_scm_get_version(void) { return 0; }
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static inline u32
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qcom_scm_set_remote_state(u32 state,u32 id) { return -ENODEV; }
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static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) { return -ENODEV; }
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static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) { return -ENODEV; }
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static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) { return -ENODEV; }
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static inline int qcom_scm_qsmmu500_wait_safe_toggle(bool en) { return -ENODEV; }
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static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) { return -ENODEV; }
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static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) { return -ENODEV; }
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u32 *resp) { return -ENODEV; }
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static inline int qcom_scm_qsmmu500_wait_safe_toggle(bool en)
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{ return -ENODEV; }
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#endif
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#endif
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