dmaengine updates for 4.13-rc1
- removal of AVR32 support in dw driver as AVR32 is gone - new driver for Broadcom stream buffer accelerator (SBA) RAID driver - add support for Faraday Technology FTDMAC020 in amba-pl08x driver - IOMMU support in pl330 driver - updates to bunch of drivers -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJZYG73AAoJEHwUBw8lI4NH+DoP/1f0TsYrQFCjNqa4nybjU1Sd bbqnpouuJscwt8Qk2LGuSimi0QG91gQOLvrmueFbXtEg86nPOfa0RnWGNF4qwYFK oliDlXF2PnV65J5kl7CvqXCj6bFiXCULVdO9JD2HFoFB1+lzXN9JQqOG5ne29BQ6 g3HNRlUTXNzQXWisgbAOLxuuvyfv68Zo3wCLYLkd4vC/C4zmxM+KXUG8+s0hS7t3 AOUpYW6F/C+y1Ax+SiACm0QGNZ4rc6/+ZUIIXUO5CfTYGjv6QUdzxiLHtc4br25l 2CoN9IP4V/OxHaW9T1jA61TeAAFr63oXYfDMBBzclzVryZRAIU72ups31uRQXpFz 99zUQ0OsdOCvy0oPInhNd8u+cpyh/4e2RDgSZ9rxw3xVaKFh8lsw5OtcCBQzCMeI xgFCUBHsLjEi4uafJcl6n2T7+Y4Y0KgOmxPHZo3tpq/2a5M6tVy8k68m3afCQylF 1SOxzVZdDRUutPpviQWop6RgP0EcVuzaUJ0vO4nat4j77vuimaPqdk+oLV46XP2d 5I52kcvbVI4BbJavTjVs3FRdcez0pW37iOw+5MOxHE3dnBp4X/3btFzBY4aOsdg0 wVut3B+9U4WHDBF2ConBxxMvGqMYmcssOQ096GdC6oBHHS7x6n7tEVPiZ5iUacn5 LB8k9AZtpBC7nUWPH7FS =srPZ -----END PGP SIGNATURE----- Merge tag 'dmaengine-4.13-rc1' of git://git.infradead.org/users/vkoul/slave-dma Pull dmaengine updates from Vinod Koul: - removal of AVR32 support in dw driver as AVR32 is gone - new driver for Broadcom stream buffer accelerator (SBA) RAID driver - add support for Faraday Technology FTDMAC020 in amba-pl08x driver - IOMMU support in pl330 driver - updates to bunch of drivers * tag 'dmaengine-4.13-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (36 commits) dmaengine: qcom_hidma: correct API violation for submit dmaengine: zynqmp_dma: Remove max len check in zynqmp_dma_prep_memcpy dmaengine: tegra-apb: Really fix runtime-pm usage dmaengine: fsl_raid: make of_device_ids const. dmaengine: qcom_hidma: allow ACPI/DT parameters to be overridden dmaengine: fsldma: set BWC, DAHTS and SAHTS values correctly dmaengine: Kconfig: Simplify the help text for MXS_DMA dmaengine: pl330: Delete unused functions dmaengine: Replace WARN_TAINT_ONCE() with pr_warn_once() dmaengine: Kconfig: Extend the dependency for MXS_DMA dmaengine: mxs: Use %zu for printing a size_t variable dmaengine: ste_dma40: Cleanup scatterlist layering violations dmaengine: imx-dma: cleanup scatterlist layering violations dmaengine: use proper name for the R-Car SoC dmaengine: imx-sdma: Fix compilation warning. dmaengine: imx-sdma: Handle return value of clk_prepare_enable dmaengine: pl330: Add IOMMU support to slave tranfers dmaengine: DW DMAC: Handle return value of clk_prepare_enable dmaengine: pl08x: use GENMASK() to create bitmasks dmaengine: pl08x: Add support for Faraday Technology FTDMAC020 ...
This commit is contained in:
Linus Torvalds
commit
2ceedf97ae
34 changed files with 3027 additions and 444 deletions
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@ -44,7 +44,14 @@
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#define PL080_SYNC (0x34)
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/* Per channel configuration registers */
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/* The Faraday Technology FTDMAC020 variant registers */
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#define FTDMAC020_CH_BUSY (0x20)
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/* Identical to PL080_CONFIG */
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#define FTDMAC020_CSR (0x24)
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/* Identical to PL080_SYNC */
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#define FTDMAC020_SYNC (0x2C)
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#define FTDMAC020_REVISION (0x30)
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#define FTDMAC020_FEATURE (0x34)
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/* Per channel configuration registers */
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#define PL080_Cx_BASE(x) ((0x100 + (x * 0x20)))
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@ -55,13 +62,20 @@
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#define PL080_CH_CONFIG (0x10)
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#define PL080S_CH_CONTROL2 (0x10)
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#define PL080S_CH_CONFIG (0x14)
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/* The Faraday FTDMAC020 derivative shuffles the registers around */
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#define FTDMAC020_CH_CSR (0x00)
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#define FTDMAC020_CH_CFG (0x04)
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#define FTDMAC020_CH_SRC_ADDR (0x08)
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#define FTDMAC020_CH_DST_ADDR (0x0C)
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#define FTDMAC020_CH_LLP (0x10)
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#define FTDMAC020_CH_SIZE (0x14)
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#define PL080_LLI_ADDR_MASK (0x3fffffff << 2)
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#define PL080_LLI_ADDR_MASK GENMASK(31, 2)
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#define PL080_LLI_ADDR_SHIFT (2)
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#define PL080_LLI_LM_AHB2 BIT(0)
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#define PL080_CONTROL_TC_IRQ_EN BIT(31)
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#define PL080_CONTROL_PROT_MASK (0x7 << 28)
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#define PL080_CONTROL_PROT_MASK GENMASK(30, 28)
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#define PL080_CONTROL_PROT_SHIFT (28)
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#define PL080_CONTROL_PROT_CACHE BIT(30)
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#define PL080_CONTROL_PROT_BUFF BIT(29)
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@ -70,16 +84,16 @@
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#define PL080_CONTROL_SRC_INCR BIT(26)
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#define PL080_CONTROL_DST_AHB2 BIT(25)
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#define PL080_CONTROL_SRC_AHB2 BIT(24)
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#define PL080_CONTROL_DWIDTH_MASK (0x7 << 21)
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#define PL080_CONTROL_DWIDTH_MASK GENMASK(23, 21)
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#define PL080_CONTROL_DWIDTH_SHIFT (21)
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#define PL080_CONTROL_SWIDTH_MASK (0x7 << 18)
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#define PL080_CONTROL_SWIDTH_MASK GENMASK(20, 18)
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#define PL080_CONTROL_SWIDTH_SHIFT (18)
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#define PL080_CONTROL_DB_SIZE_MASK (0x7 << 15)
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#define PL080_CONTROL_DB_SIZE_MASK GENMASK(17, 15)
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#define PL080_CONTROL_DB_SIZE_SHIFT (15)
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#define PL080_CONTROL_SB_SIZE_MASK (0x7 << 12)
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#define PL080_CONTROL_SB_SIZE_MASK GENMASK(14, 12)
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#define PL080_CONTROL_SB_SIZE_SHIFT (12)
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#define PL080_CONTROL_TRANSFER_SIZE_MASK (0xfff << 0)
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#define PL080S_CONTROL_TRANSFER_SIZE_MASK (0x1ffffff << 0)
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#define PL080_CONTROL_TRANSFER_SIZE_MASK GENMASK(11, 0)
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#define PL080S_CONTROL_TRANSFER_SIZE_MASK GENMASK(24, 0)
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#define PL080_CONTROL_TRANSFER_SIZE_SHIFT (0)
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#define PL080_BSIZE_1 (0x0)
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@ -102,11 +116,11 @@
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#define PL080_CONFIG_LOCK BIT(16)
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#define PL080_CONFIG_TC_IRQ_MASK BIT(15)
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#define PL080_CONFIG_ERR_IRQ_MASK BIT(14)
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#define PL080_CONFIG_FLOW_CONTROL_MASK (0x7 << 11)
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#define PL080_CONFIG_FLOW_CONTROL_MASK GENMASK(13, 11)
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#define PL080_CONFIG_FLOW_CONTROL_SHIFT (11)
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#define PL080_CONFIG_DST_SEL_MASK (0xf << 6)
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#define PL080_CONFIG_DST_SEL_MASK GENMASK(9, 6)
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#define PL080_CONFIG_DST_SEL_SHIFT (6)
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#define PL080_CONFIG_SRC_SEL_MASK (0xf << 1)
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#define PL080_CONFIG_SRC_SEL_MASK GENMASK(4, 1)
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#define PL080_CONFIG_SRC_SEL_SHIFT (1)
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#define PL080_CONFIG_ENABLE BIT(0)
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@ -119,6 +133,73 @@
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#define PL080_FLOW_PER2MEM_PER (0x6)
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#define PL080_FLOW_SRC2DST_SRC (0x7)
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#define FTDMAC020_CH_CSR_TC_MSK BIT(31)
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/* Later versions have a threshold in bits 24..26, */
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#define FTDMAC020_CH_CSR_FIFOTH_MSK GENMASK(26, 24)
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#define FTDMAC020_CH_CSR_FIFOTH_SHIFT (24)
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#define FTDMAC020_CH_CSR_CHPR1_MSK GENMASK(23, 22)
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#define FTDMAC020_CH_CSR_PROT3 BIT(21)
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#define FTDMAC020_CH_CSR_PROT2 BIT(20)
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#define FTDMAC020_CH_CSR_PROT1 BIT(19)
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#define FTDMAC020_CH_CSR_SRC_SIZE_MSK GENMASK(18, 16)
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#define FTDMAC020_CH_CSR_SRC_SIZE_SHIFT (16)
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#define FTDMAC020_CH_CSR_ABT BIT(15)
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#define FTDMAC020_CH_CSR_SRC_WIDTH_MSK GENMASK(13, 11)
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#define FTDMAC020_CH_CSR_SRC_WIDTH_SHIFT (11)
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#define FTDMAC020_CH_CSR_DST_WIDTH_MSK GENMASK(10, 8)
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#define FTDMAC020_CH_CSR_DST_WIDTH_SHIFT (8)
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#define FTDMAC020_CH_CSR_MODE BIT(7)
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/* 00 = increase, 01 = decrease, 10 = fix */
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#define FTDMAC020_CH_CSR_SRCAD_CTL_MSK GENMASK(6, 5)
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#define FTDMAC020_CH_CSR_SRCAD_CTL_SHIFT (5)
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#define FTDMAC020_CH_CSR_DSTAD_CTL_MSK GENMASK(4, 3)
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#define FTDMAC020_CH_CSR_DSTAD_CTL_SHIFT (3)
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#define FTDMAC020_CH_CSR_SRC_SEL BIT(2)
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#define FTDMAC020_CH_CSR_DST_SEL BIT(1)
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#define FTDMAC020_CH_CSR_EN BIT(0)
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/* FIFO threshold setting */
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#define FTDMAC020_CH_CSR_FIFOTH_1 (0x0)
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#define FTDMAC020_CH_CSR_FIFOTH_2 (0x1)
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#define FTDMAC020_CH_CSR_FIFOTH_4 (0x2)
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#define FTDMAC020_CH_CSR_FIFOTH_8 (0x3)
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#define FTDMAC020_CH_CSR_FIFOTH_16 (0x4)
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/* The FTDMAC020 supports 64bit wide transfers */
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#define FTDMAC020_WIDTH_64BIT (0x3)
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/* Address can be increased, decreased or fixed */
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#define FTDMAC020_CH_CSR_SRCAD_CTL_INC (0x0)
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#define FTDMAC020_CH_CSR_SRCAD_CTL_DEC (0x1)
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#define FTDMAC020_CH_CSR_SRCAD_CTL_FIXED (0x2)
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#define FTDMAC020_CH_CFG_LLP_CNT_MASK GENMASK(19, 16)
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#define FTDMAC020_CH_CFG_LLP_CNT_SHIFT (16)
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#define FTDMAC020_CH_CFG_BUSY BIT(8)
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#define FTDMAC020_CH_CFG_INT_ABT_MASK BIT(2)
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#define FTDMAC020_CH_CFG_INT_ERR_MASK BIT(1)
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#define FTDMAC020_CH_CFG_INT_TC_MASK BIT(0)
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/* Inside the LLIs, the applicable CSR fields are mapped differently */
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#define FTDMAC020_LLI_TC_MSK BIT(28)
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#define FTDMAC020_LLI_SRC_WIDTH_MSK GENMASK(27, 25)
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#define FTDMAC020_LLI_SRC_WIDTH_SHIFT (25)
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#define FTDMAC020_LLI_DST_WIDTH_MSK GENMASK(24, 22)
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#define FTDMAC020_LLI_DST_WIDTH_SHIFT (22)
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#define FTDMAC020_LLI_SRCAD_CTL_MSK GENMASK(21, 20)
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#define FTDMAC020_LLI_SRCAD_CTL_SHIFT (20)
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#define FTDMAC020_LLI_DSTAD_CTL_MSK GENMASK(19, 18)
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#define FTDMAC020_LLI_DSTAD_CTL_SHIFT (18)
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#define FTDMAC020_LLI_SRC_SEL BIT(17)
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#define FTDMAC020_LLI_DST_SEL BIT(16)
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#define FTDMAC020_LLI_TRANSFER_SIZE_MASK GENMASK(11, 0)
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#define FTDMAC020_LLI_TRANSFER_SIZE_SHIFT (0)
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#define FTDMAC020_CFG_LLP_CNT_MASK GENMASK(19, 16)
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#define FTDMAC020_CFG_LLP_CNT_SHIFT (16)
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#define FTDMAC020_CFG_BUSY BIT(8)
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#define FTDMAC020_CFG_INT_ABT_MSK BIT(2)
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#define FTDMAC020_CFG_INT_ERR_MSK BIT(1)
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#define FTDMAC020_CFG_INT_TC_MSK BIT(0)
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/* DMA linked list chain structure */
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struct pl080_lli {
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@ -47,8 +47,6 @@ enum {
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* devices with static assignments
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* @muxval: a number usually used to poke into some mux regiser to
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* mux in the signal to this channel
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* @cctl_memcpy: options for the channel control register for memcpy
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* *** not used for slave channels ***
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* @addr: source/target address in physical memory for this DMA channel,
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* can be the address of a FIFO register for burst requests for example.
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* This can be left undefined if the PrimeCell API is used for configuring
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@ -63,12 +61,28 @@ struct pl08x_channel_data {
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int min_signal;
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int max_signal;
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u32 muxval;
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u32 cctl_memcpy;
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dma_addr_t addr;
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bool single;
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u8 periph_buses;
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};
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enum pl08x_burst_size {
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PL08X_BURST_SZ_1,
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PL08X_BURST_SZ_4,
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PL08X_BURST_SZ_8,
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PL08X_BURST_SZ_16,
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PL08X_BURST_SZ_32,
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PL08X_BURST_SZ_64,
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PL08X_BURST_SZ_128,
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PL08X_BURST_SZ_256,
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};
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enum pl08x_bus_width {
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PL08X_BUS_WIDTH_8_BITS,
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PL08X_BUS_WIDTH_16_BITS,
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PL08X_BUS_WIDTH_32_BITS,
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};
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/**
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* struct pl08x_platform_data - the platform configuration for the PL08x
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* PrimeCells.
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@ -76,6 +90,11 @@ struct pl08x_channel_data {
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* platform, all inclusive, including multiplexed channels. The available
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* physical channels will be multiplexed around these signals as they are
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* requested, just enumerate all possible channels.
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* @num_slave_channels: number of elements in the slave channel array
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* @memcpy_burst_size: the appropriate burst size for memcpy operations
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* @memcpy_bus_width: memory bus width
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* @memcpy_prot_buff: whether memcpy DMA is bufferable
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* @memcpy_prot_cache: whether memcpy DMA is cacheable
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* @get_xfer_signal: request a physical signal to be used for a DMA transfer
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* immediately: if there is some multiplexing or similar blocking the use
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* of the channel the transfer can be denied by returning less than zero,
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@ -90,7 +109,10 @@ struct pl08x_channel_data {
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struct pl08x_platform_data {
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struct pl08x_channel_data *slave_channels;
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unsigned int num_slave_channels;
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struct pl08x_channel_data memcpy_channel;
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enum pl08x_burst_size memcpy_burst_size;
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enum pl08x_bus_width memcpy_bus_width;
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bool memcpy_prot_buff;
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bool memcpy_prot_cache;
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int (*get_xfer_signal)(const struct pl08x_channel_data *);
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void (*put_xfer_signal)(const struct pl08x_channel_data *, int);
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u8 lli_buses;
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@ -142,6 +142,7 @@ int raid6_select_algo(void);
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extern const u8 raid6_gfmul[256][256] __attribute__((aligned(256)));
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extern const u8 raid6_vgfmul[256][32] __attribute__((aligned(256)));
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extern const u8 raid6_gfexp[256] __attribute__((aligned(256)));
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extern const u8 raid6_gflog[256] __attribute__((aligned(256)));
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extern const u8 raid6_gfinv[256] __attribute__((aligned(256)));
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extern const u8 raid6_gfexi[256] __attribute__((aligned(256)));
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